/** Copyright 2021-2022 Haiku, Inc. All rights reserved.* Released under the terms of the MIT License.*/#include <asm_defs.h>#include <kernel/arch/arm64/arm_registers.h>.text/* Based on 12.1 The Translation Lookaside Buffer* ARM DEN0024A (ID050815)*/FUNCTION(_arch_mmu_invalidate_tlb_all):dsb st /* ensure write has completed*/// cmp x0, 3// b.eq el3cmp x0, 2b.eq el2cmp x0, 1b.eq el1el3:tlbi alle3dsb syisbretel2:tlbi alle2dsb syisbretel1:tlbi vmalle1dsb syisbretFUNCTION_END(_arch_mmu_invalidate_tlb_all)/* Based on Example 11-3 Cleaning to Point of Coherency* ARM DEN0024A (ID050815)*/FUNCTION(_arch_cache_clean_poc):MRS X0, CLIDR_EL1AND W3, W0, #0x07000000 // Get 2 x Level of CoherenceLSR W3, W3, #23CBZ W3, FinishedMOV W10, #0 // W10 = 2 x cache levelMOV W8, #1 // W8 = constant 0b1Loop1:ADD W2, W10, W10, LSR #1 // Calculate 3 x cache levelLSR W1, W0, W2 // extract 3-bit cache type for this levelAND W1, W1, #0x7CMP W1, #2B.LT Skip // No data or unified cache at this levelMSR CSSELR_EL1, X10 // Select this cache levelISB // Synchronize change of CSSELRMRS X1, CCSIDR_EL1 // Read CCSIDRAND W2, W1, #7 // W2 = log2(linelen)-4ADD W2, W2, #4 // W2 = log2(linelen)UBFX W4, W1, #3, #10 // W4 = max way number, right alignedCLZ W5, W4 /* W5 = 32-log2(ways), bit position of way in DC operand */LSL W9, W4, W5 /* W9 = max way number, aligned to position in DC operand */LSL W16, W8, W5 // W16 = amount to decrement way number per iterationLoop2:UBFX W7, W1, #13, #15 // W7 = max set number, right alignedLSL W7, W7, W2 /* W7 = max set number, aligned to position in DC operand */LSL W17, W8, W2 // W17 = amount to decrement set number per iterationLoop3:ORR W11, W10, W9 // W11 = combine way number and cache number...ORR W11, W11, W7 // ... and set number for DC operandDC CSW, X11 // Do data cache clean by set and waySUBS W7, W7, W17 // Decrement set numberB.GE Loop3SUBS X9, X9, X16 // Decrement way numberB.GE Loop2Skip:ADD W10, W10, #2 // Increment 2 x cache levelCMP W3, W10DSB sy /* Ensure completion of previous cache maintenance operation */B.GT Loop1Finished:retFUNCTION_END(_arch_cache_clean_poc)