Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
2007 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef PPC_H
#define PPC_H
typedef unsigned long ppc_cpu_t;
struct powerpc_opcode
{
const char *name;
operands are zeroes. */
unsigned long opcode;
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned long mask;
specific processors support the instructions. The defined values
are listed below. */
ppc_cpu_t flags;
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[8];
};
in the order in which the disassembler should consider
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
#define PPC_OPCODE_PPC 1
#define PPC_OPCODE_POWER 2
#define PPC_OPCODE_POWER2 4
#define PPC_OPCODE_32 8
#define PPC_OPCODE_64 0x10
is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
but it also supports many additional POWER instructions. */
#define PPC_OPCODE_601 0x20
(ie, compiler's -mcpu=common or assembler's -mcom). */
#define PPC_OPCODE_COMMON 0x40
for the assembler's -many option, and it eliminates duplicates). */
#define PPC_OPCODE_ANY 0x80
#define PPC_OPCODE_64_BRIDGE 0x100
#define PPC_OPCODE_ALTIVEC 0x200
#define PPC_OPCODE_403 0x400
#define PPC_OPCODE_BOOKE 0x800
#define PPC_OPCODE_BOOKE64 0x1000
#define PPC_OPCODE_440 0x2000
#define PPC_OPCODE_POWER4 0x4000
#define PPC_OPCODE_NOPOWER4 0x8000
#define PPC_OPCODE_CLASSIC 0x10000
#define PPC_OPCODE_SPE 0x20000
#define PPC_OPCODE_ISEL 0x40000
#define PPC_OPCODE_EFS 0x80000
#define PPC_OPCODE_BRLOCK 0x100000
#define PPC_OPCODE_PMR 0x200000
#define PPC_OPCODE_CACHELCK 0x400000
#define PPC_OPCODE_RFMCI 0x800000
#define PPC_OPCODE_POWER5 0x1000000
#define PPC_OPCODE_E300 0x2000000
#define PPC_OPCODE_POWER6 0x4000000
#define PPC_OPCODE_CELL 0x8000000
#define PPC_OPCODE_PPCPS 0x10000000
#define PPC_OPCODE_E500MC 0x20000000
#define PPC_OPCODE_405 0x40000000
#define PPC_OPCODE_VSX 0x80000000
#define PPC_OP(i) (((i) >> 26) & 0x3f)
struct powerpc_operand
{
unsigned int bitm;
-1 to indicate that BITM and SHIFT cannot be used to determine
where the operand goes in the insn. */
int shift;
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & o->bitm) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the operand value).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (*insert)
(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = (i >> o->shift) & o->bitm;
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
sign_extend (op);
(i is the instruction, o is a pointer to this structure, and op
is the result).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
unsigned long flags;
};
the operands field of the powerpc_opcodes table. */
extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
#define PPC_OPERAND_SIGNED (0x1)
range of values when running in 32 bit mode. That is, if bits is
16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
this flag is ignored. */
#define PPC_OPERAND_SIGNOPT (0x2)
is used to support extended mnemonics such as mr, for which two
operands fields are identical. The assembler should call the
insert function with any op value. The disassembler should call
the extract function, ignore the return value, and check the value
placed in the valid argument. */
#define PPC_OPERAND_FAKE (0x4)
separated from this one by a comma. This is used for the load and
store instructions which want their operands to look like
reg,displacement(reg)
*/
#define PPC_OPERAND_PARENS (0x8)
are
lt 0 gt 1 eq 2 so 3 un 3
cr0 0 cr1 1 cr2 2 cr3 3
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
#define PPC_OPERAND_CR (0x10)
register names with a leading 'r'. */
#define PPC_OPERAND_GPR (0x20)
#define PPC_OPERAND_GPR_0 (0x40)
prints these with a leading 'f'. */
#define PPC_OPERAND_FPR (0x80)
prints these symbolically if possible. */
#define PPC_OPERAND_RELATIVE (0x100)
prints these symbolically if possible. */
#define PPC_OPERAND_ABSOLUTE (0x200)
example, in the optional BF field in the comparison instructions. The
assembler must count the number of operands remaining on the line,
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
print this operand out only if it is not zero. */
#define PPC_OPERAND_OPTIONAL (0x400)
is omitted, then for the next operand use this operand value plus
1, ignoring the next operand field for the opcode. This wretched
hack is needed because the Power rotate instructions can take
either 4 or 5 operands. The disassembler should print this operand
out regardless of the PPC_OPERAND_OPTIONAL field. */
#define PPC_OPERAND_NEXT (0x800)
purposes of overflow checking (i.e., the normal most negative
number is disallowed and one more than the normal most positive
number is allowed). This flag will only be set for a signed
operand. */
#define PPC_OPERAND_NEGATIVE (0x1000)
prints these with a leading 'v'. */
#define PPC_OPERAND_VR (0x2000)
#define PPC_OPERAND_DS (0x4000)
#define PPC_OPERAND_DQ (0x8000)
#define PPC_OPERAND_PLUS1 (0x10000)
#define PPC_OPERAND_FSL (0x20000)
#define PPC_OPERAND_FCR (0x40000)
#define PPC_OPERAND_UDI (0x80000)
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
with the operands table for simplicity. The macro table is an
array of struct powerpc_macro. */
struct powerpc_macro
{
const char *name;
unsigned int operands;
specific processors support the instructions. The values are the
same as those for the struct powerpc_opcode flags field. */
ppc_cpu_t flags;
Each %N in the string is replaced with operand number N (zero
based). */
const char *format;
};
extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;
#endif
