2019-12-27 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (output_branch, output_jump,output_interseg_jump): Also emit skipped prefix warning in Intelsyntax mode. Name instruction in the warning text.* testsuite/gas/i386/mpx-inval-1.l,testsuite/gas/i386/notrackbad.l,testsuite/gas/i386/x86-64-notrackbad.l: Adjust expectations.2019-12-27 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (output_branch): Handle BND prefix the sameway as other prefixes. Emit it last before REX.(output_jump): Emit BND before REX.(output_interseg_jump): Don't emit REX.* testsuite/gas/i386/x86-64-branch-2.s,testsuite/gas/i386/x86-64-branch-3.s,testsuite/gas/i386/x86-64-mpx-branch-1.s,testsuite/gas/i386/x86-64-mpx-branch-2.s: Add REX.W cases.* testsuite/gas/i386/x86-64-mpx-branch-2.d: Match output againstx86-64-mpx-branch-1.d.* testsuite/gas/i386/x86-64-branch-2.d,testsuite/gas/i386/x86-64-branch-3.d,testsuite/gas/i386/x86-64-mpx-branch-1.d: Adjust expectations.2019-12-27 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (flip_code16): New.(output_branch, output_jump): Use it.(i386_displacement): Restrict template set to just directbranches when handling a respective operand. Don't set Disp16when in Intel64 mode and there's a respective template.* testsuite/gas/i386/i386.exp: Convert x86-64-branch-3 from listto dump test. Drop its XFail again.* testsuite/gas/i386/x86-64-branch-3.d: New.* testsuite/gas/i386/x86-64-branch-3.l: Delete.* testsuite/gas/i386/x86-64-branch-3.s: Add XBEGIN case.2019-12-27 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (i386_addressing_mode): Declare.(match_template): Don't transform displacement width flags fornon-indirect branches. Re-write transformation logic.(i386_displacement): Also check BaseIndex when deciding whetheran operand belongs to a direct branch. Restrict which DispNN getset.(i386_finalize_displacement): Set Disp8 for JumpByte templates.* config/tc-i386-intel.c (i386_intel_operand): Don't set Disp32for 64-bit addressing.* testsuite/gas/i386/i386.exp: XFail x86-64-branch-3.2019-12-17 Alan Modra <amodra@gmail.com>* doc/as.texi: Remove mention of tic80.2019-12-12 H.J. Lu <hongjiu.lu@intel.com>PR gas/25274* config/tc-i386.c (optimize_encoding): Also check R12-R15registers for "test $imm7, %r64/%r32/%r16 -> test $imm7, %r8"optimization.* testsuite/gas/i386/x86-64-optimize-3.s: Add tests for testwith r12.* testsuite/gas/i386/x86-64-optimize-3.d: Updated.* testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.2019-12-12 H.J. Lu <hongjiu.lu@intel.com>* testsuite/gas/i386/align-branch-1.s: New file.* testsuite/gas/i386/align-branch-1a.d: Likewise.* testsuite/gas/i386/align-branch-1b.d: Likewise.* testsuite/gas/i386/align-branch-1c.d: Likewise.* testsuite/gas/i386/align-branch-1d.d: Likewise.* testsuite/gas/i386/align-branch-1e.d: Likewise.* testsuite/gas/i386/align-branch-1f.d: Likewise.* testsuite/gas/i386/align-branch-1g.d: Likewise.* testsuite/gas/i386/align-branch-1h.d: Likewise.* testsuite/gas/i386/align-branch-2.s: Likewise.* testsuite/gas/i386/align-branch-2a.d: Likewise.* testsuite/gas/i386/align-branch-2b.d: Likewise.* testsuite/gas/i386/align-branch-2c.d: Likewise.* testsuite/gas/i386/align-branch-3.d: Likewise.* testsuite/gas/i386/align-branch-3.s: Likewise.* testsuite/gas/i386/align-branch-4.s: Likewise.* testsuite/gas/i386/align-branch-4a.d: Likewise.* testsuite/gas/i386/align-branch-4b.d: Likewise.* testsuite/gas/i386/align-branch-5.d: Likewise.* testsuite/gas/i386/align-branch-5.s: Likewise.* testsuite/gas/i386/align-branch-6.d: Likewise.* testsuite/gas/i386/align-branch-6.s: Likewise.* testsuite/gas/i386/align-branch-7.d: Likewise.* testsuite/gas/i386/align-branch-7.s: Likewise.* testsuite/gas/i386/align-branch-8.d: Likewise.* testsuite/gas/i386/align-branch-8.s: Likewise.* testsuite/gas/i386/x86-64-align-branch-1.s: Likewise.* testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-1e.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-1f.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-1h.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-2.s: Likewise.* testsuite/gas/i386/x86-64-align-branch-2a.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-2b.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-3.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-3.s: Likewise.* testsuite/gas/i386/x86-64-align-branch-4.s: Likewise.* testsuite/gas/i386/x86-64-align-branch-4a.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-4b.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-5.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-6.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-7.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-7.s: Likewise.* testsuite/gas/i386/x86-64-align-branch-8.d: Likewise.* testsuite/gas/i386/x86-64-align-branch-8.s: Likewise.* testsuite/gas/i386/i386.exp: Run new tests.2019-12-12 H.J. Lu <hongjiu.lu@intel.com>* config/tc-i386.c (OPTION_MBRANCHES_WITH_32B_BOUNDARIES): New.(md_longopts): Add -mbranches-within-32B-boundaries.(md_parse_option): Handle -mbranches-within-32B-boundaries.(md_show_usage): Add -mbranches-within-32B-boundaries.2019-12-12 H.J. Lu <hongjiu.lu@intel.com>* config/tc-i386.c (_i386_insn): Add has_gotpc_tls_reloc.(tls_get_addr): New.(last_insn): New.(align_branch_power): New.(align_branch_kind): New.(align_branch_bit): New.(align_branch): New.(MAX_FUSED_JCC_PADDING_SIZE): New.(align_branch_prefix_size): New.(BRANCH_PADDING): New.(BRANCH_PREFIX): New.(FUSED_JCC_PADDING): New.(i386_generate_nops): Support BRANCH_PADDING and FUSED_JCC_PADDING.(md_begin): Abort if align_branch_prefix_size <MAX_FUSED_JCC_PADDING_SIZE.(md_assemble): Set last_insn.(maybe_fused_with_jcc_p): New.(add_fused_jcc_padding_frag_p): New.(add_branch_prefix_frag_p): New.(add_branch_padding_frag_p): New.(output_insn): Generate a BRANCH_PADDING, FUSED_JCC_PADDING orBRANCH_PREFIX frag and terminate each frag to align branches.(output_disp): Set i.has_gotpc_tls_reloc to TRUE for GOTPC andrelaxable TLS relocations.(output_imm): Likewise.(i386_next_non_empty_frag): New.(i386_next_jcc_frag): New.(i386_classify_machine_dependent_frag): New.(i386_branch_padding_size): New.(i386_generic_table_relax_frag): New.(md_estimate_size_before_relax): Handle COND_JUMP_PADDING,FUSED_JCC_PADDING and COND_JUMP_PREFIX frags.(md_convert_frag): Handle BRANCH_PADDING, BRANCH_PREFIX andFUSED_JCC_PADDING frags.(OPTION_MALIGN_BRANCH_BOUNDARY): New.(OPTION_MALIGN_BRANCH_PREFIX_SIZE): New.(OPTION_MALIGN_BRANCH): New.(md_longopts): Add -malign-branch-boundary=,-malign-branch-prefix-size= and -malign-branch=.(md_parse_option): Handle -malign-branch-boundary=,-malign-branch-prefix-size= and -malign-branch=.(md_show_usage): Display -malign-branch-boundary=,-malign-branch-prefix-size= and -malign-branch=.(i386_target_format): Set tls_get_addr.(i386_cons_align): New.* config/tc-i386.h (i386_cons_align): New.(md_cons_align): New.(i386_generic_table_relax_frag): New.(md_generic_table_relax_frag): New.(i386_tc_frag_data): Add u, padding_address, length,max_prefix_length, prefix_length, default_prefix, cmp_size,classified and branch_type.(TC_FRAG_INIT): Initialize u, padding_address, length,max_prefix_length, prefix_length, default_prefix, cmp_size,classified and branch_type.* doc/c-i386.texi: Document -malign-branch-boundary=,-malign-branch= and -malign-branch-prefix-size=.2019-12-12 H.J. Lu <hongjiu.lu@intel.com>* write.c (md_generic_table_relax_frag): New. Defined torelax_frag if not defined.(relax_segment): Call md_generic_table_relax_frag instead ofrelax_frag.2019-12-12 Alan Modra <amodra@gmail.com>* config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow.* config/tc-metag.c (parse_dalu): Likewise.* config/tc-tic4x.c (md_pcrel_from): Likewise.* config/tc-tic6x.c (tic6x_output_unwinding): Likewise.* config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer.Don't use register keyword. Avoid signed overflow and remove nowunneccesary char masks. Formatting.* config/tc-ia64.c (operand_match): Don't use shifts to sign extend.* config/tc-mep.c (mep_apply_fix): Likewise.* config/tc-pru.c (md_apply_fix): Likewise.* config/tc-riscv.c (load_const): Likewise.* config/tc-nios2.c (md_apply_fix): Likewise. Don't potentiallytruncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16calculation.2019-12-12 Alan Modra <amodra@gmail.com>* config/obj-evax.c (crc32, encode_32, encode_16, decode_16):Remove unnecessary prototypes.(number_of_codings): Delete, use ARRAY_SIZE instead throughout.(codings, decodings): Make arrays of unsigned char.(crc32): Use unsigned variables. Delete unnecessary mask.(encode_32, encode_16): Return unsigned char*, and make staticbuffer an unsigned char array.(decode_16): Make arg an unsigned char*. Remove useless casts.(shorten_identifier): Use unsigned char crc_chars.(is_truncated_identifier): Make ptr an unsigned char*.2019-12-11 Wilco Dijkstra <wdijkstr@arm.com>* config/tc-arm.c (warn_on_restrict_it): Add new variable.(it_fsm_post_encode): Check warn_on_restrict_it.(arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it.* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it.* testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise.* testsuite/gas/arm/armv8-a-bad.d: Likewise.* testsuite/gas/arm/armv8-a-it-bad.d: Likewise.* testsuite/gas/arm/armv8-r-bad.d: Likewise.* testsuite/gas/arm/armv8-r-it-bad.d: Likewise.* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise.* testsuite/gas/arm/udf.d: Likewise.2018-12-11 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (md_assemble): Extend SSE check conditional.* testsuite/gas/i386/sse-check.s: Add SSE4a and SHA tests.Extend GFNI tests.* testsuite/gas/i386/sse-check.d: Adjust expectations.* testsuite/gas/i386/sse-check-error.l,testsuite/gas/i386/x86-64-sse-check-error.l: Likewise.* testsuite/gas/i386/sse-check-warn.e: Likewise.2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.* testsuite/gas/arm/mve-arch-ext.s: New.* testsuite/gas/arm/mve-arch-ext.d: New.2019-12-09 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (O_oword_ptr): Move.(O_xmmword_ptr): Alias to O_oword_ptr.(O_fword_ptr, O_tbyte_ptr, O_ymmword_ptr, O_zmmword_ptr): Adjustexpansion.(i386_intel_simplify, i386_intel_operand): Fold O_oword_ptr andO_xmmword_ptr cases, leaving comments.2019-12-09 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (O_mmword_ptr): Define.(i386_types): Add mmword entry.(i386_intel_simplify, i386_intel_operand): Add comment.* testsuite/gas/i386/intel-expr.s: Also test mmword and zmmword.* testsuite/gas/i386/intelok.s: Also test "mmword ptr".* testsuite/gas/i386/intel-expr.d, testsuite/gas/i386/intelok.d,testsuite/gas/i386/intelok.e: Adjust expectations.2019-12-09 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (i386_intel_operand): Set "byte"attribute suffix instead of suffix for floating point insns whenhandling O_near_ptr / O_far_ptr.* testsuite/gas/i386/intelbad.s: Add FPU tests.* testsuite/gas/i386/intelbad.l: Adjust expectations.2019-12-09 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (i386_intel_operand): Set "byte"attribute suffix instead of suffix uniformly for insns notpossibly accepting "tbyte ptr" explicitly.2019-12-09 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (i386_intel_operand): Don't set suffixfor floating point insns when handling O_fword_ptr.2019-12-09 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (i386_intel_operand): Don't specialcase LDS et al when handling O_word_ptr.2019-12-08 Alan Modra <amodra@gmail.com>* testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output.* testsuite/gas/aarch64/dgh.d: Likewise.* testsuite/gas/aarch64/f32mm.d: Likewise.* testsuite/gas/aarch64/f64mm.d: Likewise.* testsuite/gas/aarch64/i8mm.d: Likewise.* testsuite/gas/aarch64/pac_ab_key.d: Likewise.* testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.* testsuite/gas/aarch64/reloc-prel_g0.d: Likewise.* testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise.* testsuite/gas/aarch64/reloc-prel_g1.d: Likewise.* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise.* testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise.* testsuite/gas/aarch64/sve2.d: Likewise.2019-12-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* dw2gencfi.c (cfi_pseudo_table): Add cfi_negate_ra_state.* testsuite/gas/aarch64/pac_negate_ra_state.s: New file.* testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.2019-12-05 Jan Beulich <jbeulich@suse.com>* config/tc-aarch64.c (aarch64_features): Drop redundant AES andSHA2 flags from "crypto" entry.2019-12-05 Jan Beulich <jbeulich@suse.com>* config/tc-aarch64.c (aarch64_features): Make SHA2 a prereq ofSHA3.* testsuite/gas/aarch64/crypto.s* testsuite/gas/aarch64/crypto-directive.d: Refer to crypto.dfor actual output.* testsuite/gas/aarch64/illegal-crypto-nofp.l: Relaxexpectations.* testsuite/gas/aarch64/crypto-directive2.d,testsuite/gas/aarch64/crypto-directive3.d: New.2019-12-04 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (i386_intel_operand): Handle LFS et alas well as LGDT at al when processing O_tbyte_ptr.* testsuite/gas/i386/intelbad.s: Add LDS et al cases.* testsuite/gas/i386/x86-64-intel64.s,* testsuite/gas/i386/x86-64-opcode.s: Add LFS et al cases.* testsuite/gas/i386/ilp32/x86-64-intel64.d: Add -mintel64command line option and fold expectations with parent dir test.* testsuite/gas/i386/x86-64-intel64.d: Add -mintel64 commandline option and adjust expectations.* testsuite/gas/i386/intelbad.l,testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.2019-12-04 Jan Beulich <jbeulich@suse.com>* config/tc-i386-intel.c (i386_intel_operand): Also handle DWORDwith 64-bit mode branches.* testsuite/gas/i386/x86-64-jump.s: Extend Intel syntax branchoperand coverage.* testsuite/gas/i386/x86-64-jump.d: Adjust expectations.2019-12-04 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (output_insn): Don't consider Cpu* settingswhen setting GNU_PROPERTY_X86_FEATURE_2_MMX.2019-12-04 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/movdir.s: Add Intel syntax case withoperand size specifier.* testsuite/gas/i386/x86-64-movdir.s: Add Intel syntax caseswith operand size specifier and wit 32-bit operands.* testsuite/gas/i386/movdir-intel.d,testsuite/gas/i386/movdir.d,testsuite/gas/i386/x86-64-movdir-intel.d,testsuite/gas/i386/x86-64-movdir.d: Adjust expectations.2019-12-04 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (process_suffix): Arrange for insns with asingle non-GPR register operand to not have its suffix guessedfrom GPR operands. Extend DefaultSize handling to cover PUSH/POPof segment registers.* testsuite/gas/i386/general.s: Add PUSH/POP sreg to .code16gccset of insns.* testsuite/gas/i386/general.l: Adjust expectations.2019-12-04 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (process_suffix): Exclude SYSRET alongsideFLDENV et al.* testsuite/gas/i386/general.s: Expand .code16gcc set of insns.* testsuite/gas/i386/general.l: Adjust expectations.2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>* as.c (flag_dwarf_cie_version): Change initial value to -1, andupdate comment.* config/tc-riscv.c (riscv_after_parse_args): Setflag_dwarf_cie_version if it has not already been set.* dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version ifneeded.* testsuite/gas/riscv/default-cie-version.d: New file.* testsuite/gas/riscv/default-cie-version.s: New file.2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>* dw2gencfi.c (output_cie): Error on return column overflow.* testsuite/gas/riscv/cie-rtn-col-1.d: New file.* testsuite/gas/riscv/cie-rtn-col-3.d: New file.* testsuite/gas/riscv/cie-rtn-col.s: New file.2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSRnames too.* testsuite/gas/riscv/csr-dw-regnums.d: New file.* testsuite/gas/riscv/csr-dw-regnums.s: New file.2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>* config/tc-riscv.c (struct regname): Delete.(hash_reg_names): Handle value as 'void *'.2019-11-25 Andrew Pinski <apinski@marvell.com>* config/tc-aarch64.c (md_begin): Use correcthash table for uppercase version of hint.* testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase.* testsuite/gas/aarch64/system-2.d: Update.2019-11-25 Christian Eggers <ceggers@gmx.de>* as.h: Define SEC_OCTETS as SEC_ELF_OCTETS if OBJ_ELF.* dwarf2dbg.c: (dwarf2_finish): Set section flag SEC_OCTETS for.debug_line, .debug_info, .debug_abbrev, .debug_aranges, .debug_strand .debug_ranges sections.* write.c (maybe_generate_build_notes): Set section flagSEC_OCTETS for .gnu.build.attributes section.* frags.c (frag_now_fix): Don't divide by OCTETS_PER_BYTE ifSEC_OCTETS is set.* symbols.c (resolve_symbol_value): Likewise.2019-11-25 Christian Eggers <ceggers@gmx.de>* dwarf2dbg.c (out_set_addr): Revert 2019-03-13 change.(out_debug_line, out_debug_aranges, out_debug_info): Likewise.* symbols.h (symbol_set_value_now_octets, symbol_octets_p): Remove.* symbols.c (struct symbol_flags): Remove member sy_octets.(symbol_temp_new_now_octets): Don't set symbol_flags::sy_octets.(resolve_symbol_value): Revert: Return octets instead of bytes ifsy_octets is set.(symbol_set_value_now_octets): Remove.(symbol_octets_p): Remove.2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>* config/tc-arm.c (arm_ext_crc): New.(crc_ext_armv8): Remove.(insns): Rename crc_ext_armv8 to arm_ext_crc.(arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC.(armv8a_ext_table, armv8r_ext_table,arm_option_extension_value_table): Redefine the crcextension in terms of ARM_EXT2_CRC.* gas/testsuite/gas/arm/crc-ext.s: New.* gas/testsuite/gas/arm/crc-ext.d: New.2019-11-20 Alan Modra <amodra@gmail.com>PR 24944* atof-generic.c (atof_generic): Increase decimal guard digits.* testsuite/gas/i386/fp.s: Add more tests.* testsuite/gas/i386/fp.d: Update.2019-11-18 Andrew Burgess <andrew.burgess@embecosm.com>* as.c (parse_args): Parse --gdwarf-cie-version option.(flag_dwarf_cie_version): New variable.* as.h (flag_dwarf_cie_version): Declare.* dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION toflag_dwarf_cie_version.* doc/as.texi (Overview): Document --gdwarf-cie-version.* NEWS: Likewise.* testsuite/gas/cfi/cfi.exp: Add new tests.* testsuite/gas/cfi/cie-version-0.d: New file.* testsuite/gas/cfi/cie-version-1.d: New file.* testsuite/gas/cfi/cie-version-2.d: New file.* testsuite/gas/cfi/cie-version-3.d: New file.* testsuite/gas/cfi/cie-version-4.d: New file.* testsuite/gas/cfi/cie-version.s: New file.2019-11-14 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (operand_size_match, md_assemble,parse_insn, match_template, process_suffix, output_jump,output_insn, i386_displacement): Adjust jump* field use/handling.* config/tc-i386-intel.c (i386_intel_operand): Likewise.2019-11-14 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (struct _i386_insn): Add jumpabsolute field.(operand_type_match): Drop jumpabsolute use.(type_names): Remove OPERAND_TYPE_JUMPABSOLUTE entry.(process_suffix, i386_displacement): Adjust jumpabsolute uses.(match_template, i386_att_operand): Adjust jumpabsolutehandling.* config/tc-i386-intel.c (i386_intel_operand): Likewise.2019-11-14 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (operand_size_match): Adjust anysize use.2019-11-14 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/intel-cmps32.d,testsuite/gas/i386/intel-cmps64.d: Correct regexp closingparentheses placement.2019-11-14 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/intel-cmps.s,testsuite/gas/i386/intel-movs.s: Extend.* testsuite/gas/i386/intel-cmps32.d,testsuite/gas/i386/intel-cmps64.d,testsuite/gas/i386/intel-movs32.d,testsuite/gas/i386/intel-movs64.d: Adjust expectations.* testsuite/gas/i386/intel-cmps16.d,testsuite/gas/i386/intel-movs16.d: New.* testsuite/gas/i386/i386.exp: Run new tests.2019-11-12 Nelson Chu <nelson.chu@sifive.com>* testsuite/gas/riscv/insn.d: Add the f extension to -march option.2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>* config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it forboth fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstminstruction for mve_ext.(do_vfp_nsyn_pop): Move in order to enable it for bothfpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldminstruction for mve_ext.(do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks.(insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop,vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 insteadof fpu_vfp_ext_v1xd.* testsuite/gas/arm/v8_1m-mve.s: New.* testsuite/gas/arm/v8_1m-mve.d: New.2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>* gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd.* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test.* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>* config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits.(fpu_any): Remove OBJ_ELF guards.* testsuite/gas/arm/fpu-rst.s: New.* testsuite/gas/arm/fpu-rst.d: New.* testsuite/gas/arm/fpu-rst.l: New.2019-11-12 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (type_names): Remove OPERAND_TYPE_ESSEGentry.(md_assemble): Adjust isstring field use. Add assertion.(check_string): Mostly re-write.(i386_index_check): Adjust isstring field use and related code.2019-11-12 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (process_immext): Remove SSE3, SVME, andMWAITX special case logic.(process_suffix): Replace immext field uses by instance ones.* testsuite/gas/i386/arch-13.s,testsuite/gas/i386/x86-64-arch-3.s: Add CLZERO with operandcases.* testsuite/gas/i386/svme.s: Add 16-bit operand cases.* testsuite/gas/i386/x86-64-specific-reg.s: Drop FIXME comments.* testsuite/gas/i386/arch-13.d,testsuite/gas/i386/mwaitx-reg.l, testsuite/gas/i386/svme.d,testsuite/gas/i386/x86-64-arch-3.d,testsuite/gas/i386/x86-64-mwaitx-reg.l,testsuite/gas/i386/x86-64-specific-reg.l: Adjust expectations.2019-11-12 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (operand_type_set, operand_type_and,operand_type_and_not, operand_type_or, operand_type_xor): Handle"instance" field specially.(operand_size_match, md_assemble, match_template, process_suffix,check_byte_reg, check_long_reg, check_qword_reg, check_word_reg,process_operands, build_modrm_byte): Use "instance" instead of"acc" / "inoutportreg" / "shiftcount" fields.(optimize_imm): Adjust comment.2019-11-11 Jan Beulich <jbeulich@suse.com>* testsuite/gas/aarch64/illegal-sve2.s: Add smaxp/sminp caseswith mismatched 1st and 3rd operands.* testsuite/gas/aarch64/illegal-sve2.l: Adjust expectations.2019-11-08 H.J. Lu <hongjiu.lu@intel.com>PR gas/25167* config/tc-i386.c (match_template): Don't check instructionsuffix set from operand.* testsuite/gas/i386/code16.d: New file.* testsuite/gas/i386/code16.s: Likewise.* testsuite/gas/i386/i386.exp: Run code16.2019-11-08 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (optimize_encoding, build_modrm_byte,check_VecOperations, parse_real_register): Use "class" insteadof "regmask" and "regbnd" fields.2019-11-08 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (match_mem_size, operand_size_match,operand_type_register_match, pi, check_VecOperands, match_template,check_byte_reg, check_long_reg, check_qword_reg, process_operands,build_modrm_byte, parse_real_register): Use "class" instead of"regsimd" / "regmmx" fields.2019-11-08 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (pi, check_byte_reg, build_modrm_byte,parse_real_register): Use "class" instead of "control"/"debug"/"test" fields.2019-11-08 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (pi, check_byte_reg, process_operands,build_modrm_byte, i386_att_operand, parse_real_register): Use"class" instead of "sreg" field.* config/tc-i386-intel.c (i386_intel_simplify_register,i386_intel_operand): Likewise.2019-11-08 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (operand_type_set, operand_type_and,operand_type_and_not, operand_type_or, operand_type_xor): Handle"class" field specially.(anyimm): New.(operand_type_check, operand_size_match,operand_type_register_match, pi, md_assemble, is_short_form,process_suffix, check_byte_reg, check_long_reg, check_qword_reg,check_word_reg, process_operands, build_modrm_byte): Use "class"instead of "reg" field.(optimize_imm): Likewise. Reduce redundancy. Adjust calculationof "allowed".2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>* testsuite/gas/aarch64/dgh.s: New test.* testsuite/gas/aarch64/dgh.d: New test.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>* config/tc-arm.c (arm_ext_i8mm): New feature set.(do_vusdot): New.(do_vsudot): New.(do_vsmmla): New.(do_vummla): New.(insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics.(armv86a_ext_table): Add i8mm extension.(arm_extensions): Move bf16 extension to context sensitive table.(armv82a_ext_table, armv84a_ext_table, armv85a_ext_table):Move bf16 extension to context sensitive table.(armv86a_ext_table): Add i8mm extension.* doc/c-arm.texi: Document i8mm extension.* testsuite/gas/arm/i8mm.s: New test.* testsuite/gas/arm/i8mm.d: New test.* testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.(parse_operands): Add new operand.* testsuite/gas/aarch64/i8mm.s: New test.* testsuite/gas/aarch64/i8mm.d: New test.* testsuite/gas/aarch64/f32mm.s: New test.* testsuite/gas/aarch64/f32mm.d: New test.* testsuite/gas/aarch64/f64mm.s: New test.* testsuite/gas/aarch64/f64mm.d: New test.* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>2019-11-07 Barnaby Wilks <barnaby.wilks@arm.com>* config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format.* testsuite/gas/aarch64/bfloat16-directive-le.d: New test.* testsuite/gas/aarch64/bfloat16-directive-be.d: New test.* testsuite/gas/aarch64/bfloat16-directive.s: New test.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>2019-11-07 Barnaby Wilks <barnaby.wilks@arm.com>* config/tc-arm.c (md_atof): Add encoding for bfloat16* testsuite/gas/arm/bfloat16-directive-le.d: New test.* testsuite/gas/arm/bfloat16-directive-be.d: New test.* testsuite/gas/arm/bfloat16-directive.s: New test.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>2019-11-07 Barnaby Wilks <barnaby.wilks@arm.com>* as.h (atof_ieee_detail): Add prototype for atof_ieee_detail function.(atof_ieee): Move some code into the atof_ieee_detail function.(atof_ieee_detail): Add function that provides a higher level ofcontrol over generating IEEE-like numbers.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-arm.c (arm_archs): Add armv8.6-a option.(cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.* doc/c-arm.texi (-march): New armv8.6-a arch.* config/tc-arm.c (arm_ext_bf16): New feature set.(enum neon_el_type): Add NT_bfloat value.(B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoderhelpers.(BAD_BF16): New message.(parse_neon_type): Add bf16 type specifier.(enum neon_type_mask): Add N_BF16 type.(type_chk_of_el_type): Account for NT_bfloat.(el_type_of_type_chk): Account for N_BF16.(neon_three_args): Split out from neon_three_same.(neon_three_same): Part split out into neon_three_args.(CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.(do_neon_cvt_1): Account for vcvt.bf16.f32.(do_bfloat_vmla): New.(do_mve_vfma): New function to deal with the mnemonic clash between the BF16vfmat and the MVE vfma in a VPT block with a 't'rue condition.(do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.(do_vdot): New(do_vmmla): New(insns): Add vdot and vmmla mnemonics.(arm_extensions): Add "bf16" extension.* doc/c-arm.texi: Document "bf16" extension.* testsuite/gas/arm/attr-march-armv8_6-a.d: New test.* testsuite/gas/arm/bfloat16-bad.d: New test.* testsuite/gas/arm/bfloat16-bad.l: New test.* testsuite/gas/arm/bfloat16-bad.s: New test.* testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.* testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.* testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.* testsuite/gas/arm/bfloat16-neon.s: New test.* testsuite/gas/arm/bfloat16-non-neon.s: New test.* testsuite/gas/arm/bfloat16-thumb-bad.d: New test.* testsuite/gas/arm/bfloat16-thumb-bad.l: New test.* testsuite/gas/arm/bfloat16-thumb.d: New test.* testsuite/gas/arm/bfloat16-vfp.d: New test.* testsuite/gas/arm/bfloat16.d: New test.* testsuite/gas/arm/bfloat16.s: New test.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (vectype_to_qualifier): Special case theS_2H operand qualifier.* doc/c-aarch64.texi: Document bf16 extension.* testsuite/gas/aarch64/bfloat16.d: New test.* testsuite/gas/aarch64/bfloat16.s: New test.* testsuite/gas/aarch64/illegal-bfloat16.d: New test.* testsuite/gas/aarch64/illegal-bfloat16.l: New test.* testsuite/gas/aarch64/illegal-bfloat16.s: New test.* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (armv8.6-a): New arch.* doc/c-aarch64.texi (armv8.6-a): Document new arch.2019-11-07 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (cpu_arch): Add .rdpru and .mcommit entries.* doc/c-i386.texi: Mention rdpru and mcommit.* testsuite/gas/i386/arch-13.s,testsuite/gas/i386/x86-64-arch-3.s: Add mcommit and rdpru cases.* testsuite/gas/i386/arch-13.d,testsuite/gas/i386/x86-64-arch-3.d: Extend -march=. Adjustexpectations.* testsuite/gas/i386/arch-13-znver1.d: Extend -march=. Redirectexpectations to arch-13.d.* testsuite/gas/i386/arch-13-znver2.d: Redirect expectations toarch-13.d.testsuite/gas/i386/x86-64-arch-3-znver1.d: Extend -march=.2019-11-07 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/x86-64-arch-3.s: Add monitorx/mwaitx caseswith canonical operand sizes.* testsuite/gas/i386/x86-64-sse3.s: Add monitor/mwait cases withcanonical operand sizes.* testsuite/gas/i386/x86-64-arch-3-znver1.d,testsuite/gas/i386/x86-64-arch-3-znver2.d: Redirect expectationsto x86-64-arch-3.d.* testsuite/gas/i386/ilp32/x86-64-sse-noavx.d: Redirectexpectations to parent dir's x86-64-sse-noavx.d.* testsuite/gas/i386/ilp32/x86-64-sse3.d: Redirect expectationsto to parent dir's x86-64-sse3.d.* testsuite/gas/i386/x86-64-arch-3.d,testsuite/gas/i386/x86-64-mwaitx-bdver4.d,testsuite/gas/i386/x86-64-sse-noavx.d,testsuite/gas/i386/x86-64-sse3.d,testsuite/gas/i386/x86-64-suffix.d: Adjust expectations.2019-11-04 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (process_operands): Handle ShortForm insnslater, splitting out their segment register sub-form.2019-10-31 H.J. Lu <hongjiu.lu@intel.com>* testsuite/gas/i386/general.s: Add .code16gcc fldenv tests.* testsuite/gas/i386/general.l: Updated.2019-10-31 Mihail Ionescu <mihail.ionescu@arm.com>* config/tc-arm.c (selected_ctx_ext_table) New static variable.(arm_parse_arch): Set context sensitive extension table based on thechosen base architecture.(s_arm_arch_extension): Change to lookup extensions in the new contextsensitive tables.* gas/testsuite/gas/arm/mve-ext.s: New.* gas/testsuite/gas/arm/mve-ext.d: New.* gas/testsuite/gas/arm/mvefp-ext.s: New.* gas/testsuite/gas/arm/mvefp-ext.d: New.2019-10-30 Delia Burduv <Delia.Burduv@arm.com>* config/tc-aarch64.c (parse_address_main): Accept the omission ofthe immediate argument for ldraa and ldrab as a shorthand for theimmediate being 0.* testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.* testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.* testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept thewriteback form with no offset.* testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offseterror.2019-10-30 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.s,testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.s,testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.s: New.* testsuite/gas/i386/i386.exp: Run new tests.2019-10-30 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (optimize_encoding): Adjust opcodes comparedagainst. Adjust replacement opcode and clear .w.2019-10-29 Alan Modra <amodra@gmail.com>PR 25125* dw2gencfi.c (output_cfi_insn): Don't allow DW_CFA_advance_loc4to be placed in a different frag to the rs_cfa.2019-10-26 John David Anglin <danglin@gcc.gnu.org>PR gas/25121* config/tc-hppa.c (tc_gen_reloc): Cast some enums to int.(md_assemble): Likewise.2019-10-26 Alan Modra <amodra@gmail.com>PR 25125* dw2gencfi.c (output_cfi_insn): Don't output DW_CFA_advance_loc+0.* ehopt.c (eh_frame_estimate_size_before_relax): Return -1 foran advance_loc of zero.(eh_frame_relax_frag): Translate fr_subtype of 7 to size -1.(eh_frame_convert_frag): Handle fr_subtype of 7. Abort onunexpected fr_subtype.2019-10-25 Alan Modra <amodra@gmail.com>PR gas/25125PR gas/12049* write.c (relax_frag): Correct calculation of delta forpositive branches where "stretch" would make the branchnegative. Return zero immediately in that case. CorrectTC_PCREL_ADJUST comment.2019-10-16 Alan Modra <amodra@gmail.com>* config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don'tcall S_GET_VALUE multiple times for a symbol. Rearrange codeso it is obvious what is the primary sort key.(xg_order_trampoline_chain): Similarly.2019-10-15 Alan Modra <amodra@gmail.com>* config/tc-nds32.c (nds32_set_section_relocs): Use relocs and nparameters rather than equivalent sec->orelocation andsec->reloc_count. Don't sort for n <= 1. Tidy.2019-10-09 Nick Clifton <nickc@redhat.com>PR 25041* testsuite/gas/avr/pr25041.s: New test.* testsuite/gas/avr/pr25041.d: New test driver.2019-10-07 Jozef Lawrynowicz <jozef.l@mittosystems.com>* config/tc-msp430.c (md_parse_option): Set lower_data_region_onlyto FALSE if the data region is set to "upper", "either" or "none".(msp430_object_attribute): New.(md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute.(msp430_md_end): Replace hard-coded attribute values with enums.Handle data region object attribute.* doc/as.texi: Document MSP430 Data Region object attribute.* doc/c-msp430.texi: Document the .mspabi_attribute directive.* testsuite/gas/msp430/attr-430-small-bad.d: New test.* testsuite/gas/msp430/attr-430-small-bad.l: New test.* testsuite/gas/msp430/attr-430-small-good.d: New test.* testsuite/gas/msp430/attr-430-small.s: New test.* testsuite/gas/msp430/attr-430x-large-any-bad.d: New test.* testsuite/gas/msp430/attr-430x-large-any-bad.l: New test.* testsuite/gas/msp430/attr-430x-large-any-good.d: New test.* testsuite/gas/msp430/attr-430x-large-any.s: New test.* testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test.* testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test.* testsuite/gas/msp430/attr-430x-large-lower-good.d: New test.* testsuite/gas/msp430/attr-430x-large-lower.s: New test.* testsuite/gas/msp430/msp430.exp: Run new tests.2019-10-07 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (check_string): Make reported operand numberdepend on Intel syntax.* testsuite/gas/i386/intel-cmps.s,testsuite/gas/i386/intel-cmps32.d,testsuite/gas/i386/intel-cmps64.d: New.* testsuite/gas/i386/i386.exp: Run new tests.* testsuite/gas/i386/intel-movs.s: Extend.* testsuite/gas/i386/intel-movs32.d,testsuite/gas/i386/intel-movs64.d: Adjust expectations.* testsuite/gas/i386/string-bad.l: Tighten expectations.2019-09-24 Tamar Christina <tamar.christina@arm.com>PR gas/24991* config/tc-arm.c (out_of_range_p): New.(md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9,BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20,BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25* testsuite/gas/arm/pr24991.d: New test.* testsuite/gas/arm/pr24991.l: New test.* testsuite/gas/arm/pr24991.s: New test.2019-09-23 Alan Modra <amodra@gmail.com>* config/obj-ecoff.c: Include ecoff-bfd.h.* config/obj-elf.c: Likewise.2019-09-23 Alan Modra <amodra@gmail.com>* config/tc-arm.c: Include cpu-arm.h.2019-09-21 Alan Modra <amodra@gmail.com>* config/tc-i386.c (md_parse_option): Fix warning on vexwig assignment.2019-09-20 Alan Modra <amodra@gmail.com>* config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check.2018-09-20 Jan Beulich <jbeulich@suse.com>PR gas/25012* config/tc-i386.c (process_operands): Adjust handling ofPUSH/POP of segment registers.* testsuite/gas/i386/x86-64-opcode.s: Add PUSHq/POPq case with%fs/%gs operands. Add PUSHF/POPF case without suffix.* testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com>* NEWS: Add SVE2 and TME entries.2019-09-18 Alan Modra <amodra@gmail.com>* as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c,* read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c,* config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c,* config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c,* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,* config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c,* config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c,* config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c,* config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c,* config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c,* config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c,* config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c,* config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c,* config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c,* config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c,* config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c,* config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c,* config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c,* config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c,* config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c,* config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c,* config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c,* config/tc-xtensa.c, * config/tc-z8k.c: Update throughout forbfd section macro and function changes.* write.c (compress_debug): Use bfd_rename_section.2019-09-18 Alan Modra <amodra@gmail.com>* symbols.c (S_IS_LOCAL): Update bfd_get_section tobfd_asymbol_section.2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>* Makefile.in: Re-generate.* configure: Re-generate.* doc/Makefile.in: Re-generate.2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>* config/tc-riscv.c (riscv_multi_subset_supports): Handleinsn_class enum rather than subset char string.(riscv_ip): Update call to riscv_multi_subset_supports.2019-09-16 Phil Blundell <pb@pbcl.net>* Makefile.in, configure, doc/Makefile.in: Regenerated.2019-09-10 Nick Clifton <nickc@redhat.com>PR 24907* testsuite/gas/arm/pr24907.s: New test.* testsuite/gas/arm/pr24907.d: Expected disassembly.2019-09-09 Phil Blundell <pb@pbcl.net>binutils 2.33 branch created.2019-09-05 Alan Modra <amodra@gmail.com>* config/tc-ppc.c (ppc_elf_suffix): Display the relocationoperator on GOT reloc warnings/errors.2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>* config/tc-arm.c (parse_neon_mov): Add check to accept vectorregister to both the arguments in VMOV instruction.* testsuite/gas/arm/mve-vmov-1.d: Modify.* testsuite/gas/arm/mve-vmov-1.s: Likewise.* testsuite/gas/arm/mve-vorr.d: Likewise.2019-08-23 Nick Clifton <nickc@redhat.com>* po/sv.po: Updated Swedish translation.2019-08-22 Dennis Zhang <dennis.zhang@arm.com>* config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77,and Cortex-A76AE.* doc/c-arm.texi: Document new processors.* testsuite/gas/arm/cpu-cortex-a76ae.d: New test.* testsuite/gas/arm/cpu-cortex-a77.d: New test.* testsuite/gas/arm/cpu-cortex-m35p.d: New test.2019-08-22 Bosco García <jbgg.gnu@gmail.com>Nick Clifton <nickc@redhat.com>* atof-generic.c (atof_generic): Do not ignore leading zeros ifthey appear after a decimal point.* testsuite/gas/all/float.s: Extend test to include a number witha leading decimal point followed by several zeroes.* testsuite/gas/i386/fp.s: Likewise.* testsuite/gas/i386/fp.d: Update expected output.2019-08-22 Barnaby Wilks <barnaby.wilks@arm.com>* config/tc-aarch64.c: Add float16 directive and add "Hh" toacceptable float characters.* doc/c-aarch64.texi: Documentation for float16 directive.* testsuite/gas/aarch64/float16-be.d: New test.* testsuite/gas/aarch64/float16-le.d: New test.* testsuite/gas/aarch64/float16.s: New test.* NEWS: Add NEWS entry.2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly fortfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.2019-08-20 Dennis Zhang <dennis.zhang@arm.com>* NEWS: Mention the Arm and AArch64 new processors.* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,Cortex-A77, cortex-A65AE, and Cortex-A76AE.* doc/c-aarch64.texi: Document new CPUs.* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.* testsuite/gas/aarch64/nop-asm.s: New test.2019-08-19 Faraz Shahbazker <fshahbazker@wavecomp.com>* config/tc-mips.c (fix_bad_misaligned_address): New function.(fix_validate_branch): Call fix_bad_misaligned address_tocalculate the target address.(md_apply_fix): Likewise.(md_convert_frag): Update misaligned address calculation todisregard ISA mode bit.2019-08-19 Faraz Shahbazker <fshahbazker@wavecomp.com>* config/tc-mips.c (mips_move_labels): Retain ISA mode bitwhen moving labels in text segments.(mips_align): Indicate text mode when aligning labels intext segments.* gas/testsuite/gas/mips/insn-isa-mode.d: New test.* gas/testsuite/gas/mips/insn-isa-mode.s: New test source.* gas/testsuite/gas/mips/mips.exp: Run the new test.2019-08-19 Barnaby Wilks <Barnaby.Wilks@arm.com>* config/tc-arm.c (md_atof): Add precision check. Formatting.2019-08-15 Nick Clifton <nickc@redhat.com>* po/sv.po: Updated Swedish translation.2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>* config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64.(po_imm1_or_imm2_or_fail): Marco to check the immediate is either of48 or 64.(parse_operands): Add case OP_I48_I64.(do_mve_scalar_shift1): Add function to encode the MVE shiftinstructions with 4 arguments.* testsuite/gas/arm/mve-shift-bad.l: Modify.* testsuite/gas/arm/mve-shift-bad.s: Likewise.* testsuite/gas/arm/mve-shift.d: Likewise.* testsuite/gas/arm/mve-shift.s: Likewise.2019-08-12 Barnaby Wilks <barnaby.wilks@arm.com>* config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings.(md_atof): Set precision for float16 type.(arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternativeformat.(set_fp16_format): Parse a float16_format directive.(arm_parse_fp16_opt): Parse the fp16-format command line option.(aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute.* config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands toarm_is_largest_exponent_ok.(arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function.* doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format=* testsuite/gas/arm/float16-bad.d: New test.* testsuite/gas/arm/float16-bad.l: New test.* testsuite/gas/arm/float16-bad.s: New test.* testsuite/gas/arm/float16-be.d: New test.* testsuite/gas/arm/float16-format-bad.d: New test.* testsuite/gas/arm/float16-format-bad.l: New test.* testsuite/gas/arm/float16-format-bad.s: New test.* testsuite/gas/arm/float16-format-opt-bad.d: New test.* testsuite/gas/arm/float16-format-opt-bad.l: New test.* testsuite/gas/arm/float16-le.d: New test.* testsuite/gas/arm/float16.s: New test.* testsuite/gas/arm/float16-eabi-alternative-format.d: New test.* testsuite/gas/arm/float16-eabi-ieee-format.d: New test.* testsuite/gas/arm/float16-eabi-no-format.d: New test.* testsuite/gas/arm/float16-eabi.s: New test.2019-08-12 Barnaby Wilks <barnaby.wilks@arm.com>* config/atof-ieee.c (H_PRECISION): Macro for precision of float16type.(atof_ieee): Set precision and exponent bits for encoding float16types.(gen_to_words): NaN and Infinity encoding for float16.(ieee_md_atof): Set precision for encoding float16 type.2019-08-12 Alan Modra <amodra@gmail.com>PR 24851* config/tc-epiphany.c (md_estimate_size_before_relax): Clearextra opcode bytes when changing from a 2-byte to a 4-byte insn.2019-08-09 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/ilp32/x86-64-simd-intel.d,testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,testsuite/gas/i386/ilp32/x86-64-simd.d: Redirect to parent diroutput expectations.* testsuite/gas/i386/x86-64-simd-intel.d,testsuite/gas/i386/x86-64-simd-suffix.d,testsuite/gas/i386/x86-64-simd.d: Don't hard-code hex addressesand symbol-relative offsets.2019-08-08 Nick Clifton <nickc@redhat.com>PR 24887* testsuite/gas/i386/property-1.d: Adjust for new output formatfrom readelf.* testsuite/gas/i386/property-2.d: Likewise.* testsuite/gas/i386/x86-64-property-1.d: Likewise.* testsuite/gas/i386/x86-64-property-2.d: Likewise.2019-08-08 Yoshinori Sato <ysato@users.sourceforge.jp>* testsuite/gas/h8300/h8300.exp: Fix movfpe and movtpe tests.* testsuite/gas/h8300/misc.s: Likewise.* testsuite/gas/h8300/misch.s: Likewise.* testsuite/gas/h8300/miscs.s: Likewise.2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>* config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.(do_neon_qrdmlah): Use N_S_32 macro.* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.2019-07-30 Mel Chen <mel.chen@sifive.com>* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-accessalias instructions.* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with-Mno-aliases.* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.* testsuite/gas/riscv/priv-reg.d: Update.2019-07-24 Nick Clifton <nickc@redhat.com>* po/sv.po: Updated Swedish translation.2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>* testsuite/gas/arc/nps400-6.d: Update test.2019-07-24 Alan Modra <amodra@gmail.com>* config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi.* testsuite/gas/elf/section12a.d: Update xfails.* testsuite/gas/elf/section12b.d: Likewise.2019-07-24 Alan Modra <amodra@gmail.com>* testsuite/gas/elf/section12a.d: xfail visium and cloudabi.* testsuite/gas/elf/section12b.d: Likewise.* testsuite/gas/elf/section13.d: Likewise.2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* testsuite/gas/aarch64/sysreg-4.s: Test gmid_el1 read.* testsuite/gas/aarch64/sysreg-4.d: Update expected output.* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.2019-07-23 Alan Modra <amodra@gmail.com>* config/obj-elf.c (obj_elf_change_section): Don't emit a fatalerror for non-SHF_ALLOC SHF_GNU_MBIND here.(obj_elf_parse_section_letters): Return SHF_GNU_MBIND in newgnu_attr param.(obj_elf_section): Adjust obj_elf_parse_section_letters call.Formatting. Set SHF_GNU_MBIND and elf_osabi from gnu_attr.Emit normal error for non-SHF_ALLOC SHF_GNU_MBIND and wrong osabi.(obj_elf_type): Set elf_osabi for ifunc.* testsuite/gas/elf/section12a.d: xfail msp430 and hpux.* testsuite/gas/elf/section12b.d: Likewise.* testsuite/gas/elf/section13.d: Likewise.* testsuite/gas/elf/section13.l: Adjust expected error.2019-07-23 Alan Modra <amodra@gmail.com>* testsuite/gas/elf/section12a.d: Don't skip for rx.2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>* config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.* testsuite/gas/arm/mve-vqdmladh.d: New tests.* testsuite/gas/arm/mve-vqdmladh.s: New tests.* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.2019-07-19 H.J. Lu <hongjiu.lu@intel.com>* testsuite/gas/i386/noextreg.d: Pass -O0 to assembler.2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.* testsuite/gas/bpf/lddw-be.d: Likewise.* testsuite/gas/bpf/lddw.d: Likewise.* testsuite/gas/bpf/alu-be.d: Likewise.* testsuite/gas/bpf/alu32.d: Likewise.2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>* config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c.(pe_lcomm): Likewise.(md_pseudo_table): Use pe_lcomm to implement .lcomm.2019-07-19 Richard Sandiford <richard.sandiford@arm.com>* doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm.* config/tc-aarch64.c (aarch64_features): Likewise.* testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly.* testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise.* testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise.* testsuite/gas/aarch64/illegal-sve2.d: Likewise.* testsuite/gas/aarch64/sve2.d: Likewise.2019-07-19 Alan Modra <amodra@gmail.com>* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel","got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".(fixup_size, md_assemble): Handle pcrel tls relocs.(ppc_force_relocation, ppc_fix_adjustable): Likewise.(md_apply_fix, tc_gen_reloc): Likewise.2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com>* config/tc-bpf.c: Make .lcomm to get a third argument with thealignment.2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com>* config/tc-bpf.c (md_pseudo_table): .half, .word and .dword.* testsuite/gas/bpf/data.s: New file.* testsuite/gas/bpf/data.d: Likewise.* testsuite/gas/bpf/data-be.d: Likewise.* testsuite/gas/bpf/bpf.exp: Run data and data-be.* doc/c-bpf.texi (BPF Directives): New section.2019-07-17 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (check_hle, md_assemble, check_VecOperands,match_template, check_string, build_modrm_byte): Replaceoperand_type_check(..., anymem) by Operand_Mem ones.(process_operands): Also copy i.flags[] when copying otheroperand properties.2019-07-16 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (match_template): Adjust regmem reference.Adjust comment and update regmem when swapping operands.(build_modrm_byte): Drop clearing of regmem and stale part ofcomment. Correct comment. Adjust regmem reference.2019-07-16 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (type_names): Replace SReg entries.(pi, check_byte_reg, build_modrm_byte, i386_att_operand,parse_real_register): Switch to using sreg field.(process_operands): Likewise. Extend handling of PUSH/POP ofsegment registers. Drop dead setting of REX_B.* config/tc-i386-intel.c (i386_intel_simplify_register,i386_intel_operand): Switch to using sreg field.* testsuite/gas/i386/x86-64-opcode.s: Add PUSH/POP of %fs/%gs.* testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.* testsuite/gas/i386/ilp32/x86-64-opcode.d: Use parent direxpectations.2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'register as an argument.* testsuite/gas/bpf/mem.d: Updated accordingly.* testsuite/gas/bpf/mem-be.d: Likewise.* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correctexplicit arguments to ldabs and ldind instructions.2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>* testsuite/gas/bpf/mem.s: Do not use explicit arguments forldabs and ldind instructions.* testsuite/gas/bpf/mem.d: Updated accordingly.* testsuite/gas/bpf/mem-be.d: Likewise.2019-07-09 Alan Modra <amodra@gmail.com>* config/obj-elf.c (elf_frob_symbol): Remove mips hacks.* config/tc-mips.h (tc_frob_symbol): Define.(mips_frob_symbol): Declare.* config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix.(mips_frob_symbol): Fudge symbols for irix here.* testsuite/gas/elf/type-2.e: Allow random target symbols.2019-07-05 Kito Cheng <kito.cheng@sifive.com>* doc/c-riscv.texi (Instruction Formats): Add r4 type.* testsuite/gas/riscv/insn.d: Add testcase for r4 type.* testsuite/gas/riscv/insn.s: Ditto.* doc/c-riscv.texi (Instruction Formats): Add b and j type.* testsuite/gas/riscv/insn.d: Add test case for b and j type.* testsuite/gas/riscv/insn.s: Ditto.* testsuite/gas/riscv/insn.s: Correct instruction type for loadand store.* testsuite/gas/riscv/insn.d: Using regular expression to matchaddress.* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SBtype and fix typo.2019-07-04 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (md_parse_option): Don't blindly accept all-Q options.(md_show_usage): Correctly name the ignored -Q option flavors.2019-07-04 Jan Beulich <jbeulich@suse.com>* config/obj-elf.c (obj_elf_type): Check for conflicts betweenold and new types.* config/tc-hppa.h (md_elf_symbol_type_change): New.* doc/as.texi: Mention warning behavior for the ELF flavor of.type.* testsuite/gas/elf/type-2.e, testsuite/gas/elf/type-2.l,testsuite/gas/elf/type-2.s: New.* testsuite/gas/elf/elf.exp: Run new test.2019-07-03 Nick Clifton <nickc@redhat.com>* testsuite/gas/aarch64/codealign.d: Update to work with atoolchain configured to generate build notes.* testsuite/gas/aarch64/codealign_1.d: Likewise.* testsuite/gas/aarch64/dwarf.d: Likewise.* testsuite/gas/aarch64/mapmisc.d: Likewise.* testsuite/gas/aarch64/mapping.d: Likewise.* testsuite/gas/aarch64/mapping2.d: Likewise.* testsuite/gas/aarch64/mapping3.d: Likewise.* testsuite/gas/aarch64/mapping4.d: Likewise.* testsuite/gas/aarch64/mapping_5.d: Likewise.* testsuite/gas/aarch64/mapping_6.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_1.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_10.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_11.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_12.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_13.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_14.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_15.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_16.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_17.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_18.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_19.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_2.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_20.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_21.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_22.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_23.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_24.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_25.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_26.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_27.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_3.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_4.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_5.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_6.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_7.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_8.d: Likewise.* testsuite/gas/aarch64/sve-movprfx_9.d: Likewise.* testsuite/gas/aarch64/symbol-variant_pcs-1.d: Likewise.* testsuite/gas/aarch64/symbol-variant_pcs-2.d: Likewise.* testsuite/gas/aarch64/symbol-variant_pcs-3.d: Likewise.* testsuite/gas/all/assign.d: Likewise.* testsuite/gas/all/none.d: Likewise.* testsuite/gas/all/weakref1.d: Likewise.* testsuite/gas/arm/got_prel.d: Likewise.* testsuite/gas/arm/local_function.d: Likewise.* testsuite/gas/arm/mapdir.d: Likewise.* testsuite/gas/arm/mapmisc.d: Likewise.* testsuite/gas/arm/mapping2.d: Likewise.* testsuite/gas/arm/mapping3.d: Likewise.* testsuite/gas/arm/mapping4.d: Likewise.* testsuite/gas/arm/mapsecs.d: Likewise.* testsuite/gas/arm/mapshort-eabi.d: Likewise.* testsuite/gas/arm/thumbrel.d: Likewise.* testsuite/gas/arm/unwind.d: Likewise.* testsuite/gas/cfi/cfi-label.d: Likewise.* testsuite/gas/elf/elf.exp: Likewise.* testsuite/gas/i386/bss.d: Likewise.* testsuite/gas/i386/ifunc-3.d: Likewise.* testsuite/gas/i386/ilp32/mixed-mode-reloc64.d: Likewise.* testsuite/gas/i386/ilp32/quad.d: Likewise.* testsuite/gas/i386/ilp32/reloc64.d: Likewise.* testsuite/gas/i386/ilp32/x86-64-size-1.d: Likewise.* testsuite/gas/i386/ilp32/x86-64-size-3.d: Likewise.* testsuite/gas/i386/ilp32/x86-64-size-5.d: Likewise.* testsuite/gas/i386/ilp32/x86-64-unwind.d: Likewise.* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.* testsuite/gas/i386/mixed-mode-reloc64.d: Likewise.* testsuite/gas/i386/nop-6.d: Likewise.* testsuite/gas/i386/property-1.d: Likewise.* testsuite/gas/i386/property-2.d: Likewise.* testsuite/gas/i386/relax.d: Likewise.* testsuite/gas/i386/reloc64.d: Likewise.* testsuite/gas/i386/size-1.d: Likewise.* testsuite/gas/i386/size-3.d: Likewise.* testsuite/gas/i386/x86-64-nop-6.d: Likewise.* testsuite/gas/i386/x86-64-property-1.d: Likewise.* testsuite/gas/i386/x86-64-property-2.d: Likewise.* testsuite/gas/i386/x86-64-size-1.d: Likewise.* testsuite/gas/i386/x86-64-size-3.d: Likewise.* testsuite/gas/i386/x86-64-size-5.d: Likewise.* testsuite/gas/i386/x86-64-unwind.d: Likewise.* testsuite/gas/macros/irp.d: Likewise.* testsuite/gas/macros/repeat.d: Likewise.* testsuite/gas/macros/rept.d: Likewise.* testsuite/gas/macros/test2.d: Likewise.* testsuite/gas/macros/test3.d: Likewise.* testsuite/gas/macros/vararg.d: Likewise.* testsuite/gas/ppc/astest2.d: Likewise.* testsuite/gas/ppc/astest2_64.d: Likewise.* testsuite/gas/ppc/astest64.d: Likewise.* testsuite/gas/ppc/power4.d: Likewise.* testsuite/gas/ppc/test1elf64.d: Likewise.2019-07-02 Barnaby Wilks <barnaby.wilks@arm.com>* config/tc-aarch64.c (parse_operands): Add error check.* testsuite/gas/aarch64/diagnostic.l: New test.* testsuite/gas/aarch64/diagnostic.s: New test.* testsuite/gas/aarch64/illegal.l: New tests.* testsuite/gas/aarch64/illegal.s: New tests.2019-07-02 Richard Sandiford <richard.sandiford@arm.com>* testsuite/gas/aarch64/sve-movprfx_27.s,* testsuite/gas/aarch64/sve-movprfx_27.d: New test.2019-07-02 Richard Sandiford <richard.sandiford@arm.com>* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,SCVTF, UCVTF, LSR and ASR.* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.2019-07-02 Richard Sandiford <richard.sandiford@arm.com>* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1to be prefixed by MOVPRFX.* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.2019-07-01 Nick Clifton <nickc@redhat.com>PR 24748* write.c (create_note_reloc): Add desc2_offset parameter. Changename of offset parameter to note_offset. Only use desc2_offsetwhen placing addend into REL reloc's address space.(maybe_generate_build_notes): Update parameters passed tocreate_note_reloc.2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.* testsuite/gas/aarch64/illegal-sve2.l: Update tests.* doc/c-aarch64.texi: Add special note of pmull{t,b}instructions under the sve2-aes architecture extension.* testsuite/gas/aarch64/illegal-sve2.s: Add small sizepmull{t,b} instructions.* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}disassembly.* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}instructions.2019-07-01 Nick Clifton <nickc@redhat.com>PR 24738* doc/c-i386.texi (i386-Directives): Add a description of theValue directive.2019-07-01 Nick Clifton <nickc@redhat.com>PR 24737* doc/as.texi (Align): Add missing word to description ofpseudo-op.(P2align): Likewise.2019-06-28 Nick Clifton <nickc@redhat.com>PR 24735* doc/as.texi (Zero): Fix spelling typo.2019-07-01 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (vec_imm4): Delete.(VEX_check_operands): Replace Vec_Imm4 check by CpuXOP with fiveoperands one. Clear Imm<N> by different means.(build_modrm_byte): Adjust comment. Remove dead code. Add andadjust assertions.2019-07-01 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (output_insn): Adjust recognition of xFENCEinsns. Move PadLock special case of prefix emission to 3-bytelong base opcode handling.(i386_index_check): Check for CpuPadLock instead of ImmExt.2019-07-01 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (optimize_encoding): Handle AND / OR withboth operands being the same register.* doc/c-i386.texi: Update -O2 documentation.* testsuite/gas/i386/optimize-2.s,testsuite/gas/i386/x86-64-optimize-3.s: Add cases of AND / ORwith both operands being the same register.* testsuite/gas/i386/optimize-2.d,testsuite/gas/i386/x86-64-optimize-3.d: Adjust expectations.* testsuite/gas/i386/optimize-2b.d,testsuite/gas/i386/x86-64-optimize-3b.d: New.* testsuite/gas/i386/i386.exp: Run new test.2019-07-01 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (commutative): New.(build_vex_prefix): Handle commutative case.(optimize_encoding): Set commutative flag when appropriate.* doc/c-i386.texi: Update -O2 documentation.* testsuite/gas/i386/ilp32/x86-64-sse2avx.d: Re-use parent diroutput.* testsuite/gas/i386/x86-64-sse2avx.s: Add tests with highnumbered source operands.* testsuite/gas/i386/x86-64-optimize-2.d,testsuite/gas/i386/x86-64-optimize-2b.d,testsuite/gas/i386/x86-64-optimize-3.d,testsuite/gas/i386/x86-64-optimize-5.d,testsuite/gas/i386/x86-64-optimize-6.d,testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.* testsuite/gas/i386/x86-64-avx-swap-2.d,testsuite/gas/i386/x86-64-avx-swap-2.s: New.* testsuite/gas/i386/i386.exp: Run new test.2019-07-01 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (is_evex_encoding): Don't check for SAE.(check_VecOperands): Simplify static rounding / SAE checking.2019-07-01 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (optimize_encoding): Make j unsigned. Handlevpand{d,q}, vpandn{d,q}, vpor{d,q}, and vpxor{d,q}. Also check/clear broadcast. Eliminate a loop.* doc/c-i386.texi: Update -O1 documentation.* testsuite/gas/i386/optimize-1.s,testsuite/gas/i386/optimize-2.s,testsuite/gas/i386/optimize-3.s,testsuite/gas/i386/optimize-5.s,testsuite/gas/i386/x86-64-optimize-2.s,testsuite/gas/i386/x86-64-optimize-3.s,testsuite/gas/i386/x86-64-optimize-4.s,testsuite/gas/i386/x86-64-optimize-6.s: Add vpand{d,q},vpandn{d,q}, vpor{d,q}, and vpxor{d,q} cases.testsuite/gas/i386/optimize-1.d,testsuite/gas/i386/optimize-1a.d,testsuite/gas/i386/optimize-2.d,testsuite/gas/i386/optimize-3.d,testsuite/gas/i386/optimize-4.d,testsuite/gas/i386/optimize-5.d,testsuite/gas/i386/x86-64-optimize-2.d,testsuite/gas/i386/x86-64-optimize-2a.d,testsuite/gas/i386/x86-64-optimize-2b.d,testsuite/gas/i386/x86-64-optimize-3.d,testsuite/gas/i386/x86-64-optimize-4.d,testsuite/gas/i386/x86-64-optimize-5.d,testsuite/gas/i386/x86-64-optimize-6.d: Adjust expectations.2019-07-01 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/avx512f_vpclmulqdq.s,testsuite/gas/i386/avx512vl_vpclmulqdq.s,testsuite/gas/i386/vpclmulqdq.s,testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s,testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Add pseudo ops.* testsuite/gas/i386/x86-64-vpclmulqdq.s: Likewise. Don't usehigh 16 [xy]mm registers.* testsuite/gas/i386/avx512f_vpclmulqdq.d,testsuite/gas/i386/avx512f_vpclmulqdq-intel.d,testsuite/gas/i386/avx512vl_vpclmulqdq.d,testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d,testsuite/gas/i386/vpclmulqdq.d,testsuite/gas/i386/vpclmulqdq-intel.d,testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d,testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d,testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d,testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d,testsuite/gas/i386/x86-64-vpclmulqdq.d,testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Adjustexpectations.2019-07-01 Jan Beulich <jbeulich@suse.com>* tc-i386.c (output_disp, output_imm): Use encoding_length.2019-07-01 Jan Beulich <jbeulich@suse.com>* tc-i386.c (encoding_length): New.(output_insn): Use it.* testsuite/gas/i386/oversized16.l,testsuite/gas/i386/oversized16.s,testsuite/gas/i386/oversized64.l,testsuite/gas/i386/oversized64.s: New.* testsuite/gas/i386/i386.exp: Run new tests.2019-06-27 H.J. Lu <hongjiu.lu@intel.com>PR binutils/24719* testsuite/gas/i386/disassem.s: Add test for vgatherpf0dpswith invalid vector length.* testsuite/gas/i386/x86-64-disassem.s: Likewise.* testsuite/gas/i386/disassem.d: Updated.* testsuite/gas/i386/x86-64-disassem.d: Likewise.2019-06-27 Barnaby Wilk s<barnaby.wilks@arm.com>* config/tc-arm.c (do_smc): Add range check for immediate operand.(do_t_smc): Add range check for immediate operand. Removeobsolete immediate encoding.(md_apply_fix): Fix range check. Remove obsolete immediate encoding.* testsuite/gas/arm/arch6zk.d: Fix test.* testsuite/gas/arm/arch6zk.s: Fix test.* testsuite/gas/arm/smc-bad.d: New test.* testsuite/gas/arm/smc-bad.l: New test.* testsuite/gas/arm/smc-bad.s: New test.* testsuite/gas/arm/thumb32.d: Fix test.* testsuite/gas/arm/thumb32.s: Fix test.2019-06-27 Jan Beulich <jbeulich@suse.com>config/tc-i386.c (md_assemble): Check for protected modeincapable processor before encoding VEX and alike insns.* testsuite/gas/i386/inval-16.s: For 80186 architecture.* testsuite/gas/i386/inval-16.l: Adjust expectations.* testsuite/gas/i386/avx-16bit.d,testsuite/gas/i386/avx-16bit.s,testsuite/gas/i386/avx512f-16bit.d,testsuite/gas/i386/avx512f-16bit.s,testsuite/gas/i386/bmi-16bit.d,testsuite/gas/i386/bmi-16bit.s,testsuite/gas/i386/bmi2-16bit.d,testsuite/gas/i386/bmi2-16bit.s,testsuite/gas/i386/lwp-16bit.d,testsuite/gas/i386/lwp-16bit.s: Newtestsuite/gas/i386/i386.exp: Run new tests.2019-06-26 Jim Wilson <jimw@sifive.com>* testsuite/gas/xstormy16/allinsn.sh: Change first line to#!/bin/bash and make it executable.* testsuite/gas/xstormy16/gcc.sh: Likewise.2019-06-26 Lili Cui <lili.cui@intel.com>* doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&Tsyntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr inIntel syntax.2019-06-25 Faraz Shahbazker <fshahbazker@wavecomp.com>* config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 withrespect to MTC1 and use $0 for either part where possible.* testsuite/gas/mips/li-d.s: Add test cases for non-zerowords in double precision constants.* testsuite/gas/mips/li-d.d: Update reference output.* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.* testsuite/gas/mips/mips64r2@isa-override-1.d: Likewise.2019-06-25 Jan Beulich <jbeulich@suse.com>* tc-i386.c (acc32, acc64): Delete.(pi): Make first parameter pinter-to-const.(type_names): Remove Acc. Add acc8, acc16, acc32, and acc64.(pt): Use operand_type_equal().(match_template): Replace use of acc32.(process_suffix): Replace use of acc64.2019-06-25 Jan Beulich <jbeulich@suse.com>* doc/c-i386.texi: Mark -mavxscalar= and -mvexwig as dangrous touse.2019-06-25 Jan Beulich <jbeulich@suse.com>* tc-i386.c (process_suffix): Use is_any_vex_encoding().2019-06-25 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/sse2-16bit.d,testsuite/gas/i386/sse2-16bit.s: New.testsuite/gas/i386/i386.exp: Run new test.2019-06-25 Jan Beulich <jbeulich@suse.com>* config/tc-i386.c (optimize_encoding): Also handle ANDQ withimmediatie fitting in 7 bits.* testsuite/gas/i386/x86-64-optimize-1.s: Add ANDQ cases with7- and 8-bit immediates.* testsuite/gas/i386/x86-64-optimize-1.d: Adjust expectations.2019-06-25 Jan Beulich <jbeulich@suse.com>* testsuite/gas/i386/xmmword.s: Add cvtps2pi and cvttps2pitests.* testsuite/gas/i386/xmmword.l: Adjust expectations.2019-06-25 Alan Modra <amodra@gmail.com>* config/tc-ppc.c (ppc_handle_align): Add parentheses.2019-06-25 Alan Modra <amodra@gmail.com>* config/tc-ppc.h (ppc_nop_select): Declare.(NOP_OPCODE): Define.* config/tc-ppc.c (ppc_elf_end, ppc_xcoff_end): Zero ppc_cpu.(ppc_nop_encoding_for_rs_align_code): New enum.(ppc_nop_select): New function.(ppc_handle_align): Don't use ppc_cpu here. Get nop type from frag.* testsuite/gas/ppc/groupnop.d,* testsuite/gas/ppc/groupnop.s: New test.* testsuite/gas/ppc/ppc.exp: Run it.2019-06-19 H.J. Lu <hongjiu.lu@intel.com>PR binutils/24700* testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8with invalid vector length.* testsuite/gas/i386/x86-64-disassem.s: Likewise.* testsuite/gas/i386/disassem.d: Updated.* testsuite/gas/i386/x86-64-disassem.d: Likewise.2019-06-17 H.J. Lu <hongjiu.lu@intel.com>PR binutils/24691* testsuite/gas/i386/disassem.s: Add test for vshuff32x4 withinvalid vector length.* testsuite/gas/i386/x86-64-disassem.s: Likewise.* testsuite/gas/i386/disassem.d: Updated.* testsuite/gas/i386/x86-64-disassem.d: Likewise.2019-06-14 Alan Modra <amodra@gmail.com>* Makefile.in: Regenerate.* configure: Regenerate.* doc/Makefile.in: Regenerate.2019-06-12 Peter Bergner <bergner@linux.ibm.com>* testsuite/gas/ppc/power9.d: Delete ldmx tests.* testsuite/gas/ppc/power9.s: Likewise.2019-06-06 Lili Cui <lili.cui@intel.com>* config/tc-i386.c (cpu_arch): Add .enqcmd.(cpu_noarch): Add noenqcmd.* doc/c-i386.texi: Document noenqcmd.2019-06-05 H.J. Lu <hongjiu.lu@intel.com>PR binutils/24633* testsuite/gas/i386/disassem.s: Add tests for invalid vectorlengths for EVEX vextractfXX and vinsertfXX.* testsuite/gas/i386/x86-64-disassem.s: Likewise.* testsuite/gas/i386/disassem.d: Updated.* testsuite/gas/i386/x86-64-disassem.d: Likewise.2019-06-04 H.J. Lu <hongjiu.lu@intel.com>PR binutils/24626* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvvand EVEX.vvvv.* testsuite/gas/i386/x86-64-disassem.s: Likewise.* testsuite/gas/i386/disassem.d: Updated.* testsuite/gas/i386/x86-64-disassem.d: Likewise.2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>Lili Cui <lili.cui@intel.com>* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.(cpu_noarch): Likewise.* doc/c-i386.texi: Document avx512_vp2intersect.* testsuite/gas/i386/i386.exp: Run vp2intersect tests.* testsuite/gas/i386/vp2intersect-intel.d: New test.* testsuite/gas/i386/vp2intersect.d: Likewise.* testsuite/gas/i386/vp2intersect.s: Likewise.* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>Lili Cui <lili.cui@intel.com>* doc/c-i386.texi: Document enqcmd.* testsuite/gas/i386/enqcmd-intel.d: New file.* testsuite/gas/i386/enqcmd-inval.l: Likewise.* testsuite/gas/i386/enqcmd-inval.s: Likewise.* testsuite/gas/i386/enqcmd.d: Likewise.* testsuite/gas/i386/enqcmd.s: Likewise.* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,and x86-64-enqcmd.2019-05-30 Jim Wilson <jimw@sifive.com>* config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside ifstatement. Delete O_symbol and O_constant check after if statement.* testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi.* testsuite/gas/riscv/auipc-parsing.l: Update.2019-05-28 H.J. Lu <hongjiu.lu@intel.com>PR gas/24625* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16instructions with invalid broadcast.* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.* testsuite/gas/i386/inval-avx512f.l: Updated.* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.2019-05-27 Alan Modra <amodra@gmail.com>* config/tc-ppc.c (is_ppc64_target): New function.(md_show_usage): Split up usage message. Don't show -a64 whenunsupported.testsuite/gas/ppc/ppc.exp (supports_ppc64): New.(prefix-reloc): Only run for ppc64.2019-05-24 Szabolcs Nagy <szabolcs.nagy@arm.com>* config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define.* config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare.(OBJ_COPY_SYMBOL_ATTRIBUTES): Define.* testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test.* testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.2019-05-24 Szabolcs Nagy <szabolcs.nagy@arm.com>* config/tc-aarch64.c (s_variant_pcs): New function.* doc/c-aarch64.texi: Document .variant_pcs.* testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test.* testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test.* testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test.* testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.2019-05-24 Alan Modra <amodra@gmail.com>* po/POTFILES.in: Regenerate.2019-05-24 Alan Modra <amodra@gmail.com>* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.(fixup_size): Handle new powerxx relocs.(md_assemble): Warn for @pcrel on non-prefix insns.Accept @l, @h and @ha on prefix insns, and infer reloc withoutany @ suffix. Translate powerxx relocs to suit DQ and DS fieldinstructions. Include operand tests as well as opcode test totranslate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.(md_apply_fix): Handle new powerxx relocs.* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): AcceptBFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.* testsuite/gas/ppc/prefix-reloc.d,* testsuite/gas/ppc/prefix-reloc.s: New test.* testsuite/gas/ppc/ppc.exp: Run it.2019-05-24 Peter Bergner <bergner@linux.ibm.com>Alan Modra <amodra@gmail.com>* config/tc-ppc.c (ppc_insert_operand): Only sign extend fields thatare 32-bits or smaller.* messages.c (as_internal_value_out_of_range): Do not truncatevariables and use BFD_VMA_FMT to print them.* testsuite/gas/ppc/prefix-pcrel.s,* testsuite/gas/ppc/prefix-pcrel.d: New test.* testsuite/gas/ppc/ppc.exp: Run it.2019-05-24 Peter Bergner <bergner@linux.ibm.com>Alan Modra <amodra@gmail.com>* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.(struct insn_label_list): New.(insn_labels, free_insn_labels): New variables.(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.(ppc_frob_label, ppc_new_dot_label): Move functions earlier in fileand call ppc_record_label.(md_assemble): Handle 64-bit prefix instructions. Align labelsthat are on the same line as a prefix instruction.* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move tolater in the file.(md_start_line_hook): Define.(ppc_start_line_hook): Declare.* testsuite/gas/ppc/prefix-align.d,* testsuite/gas/ppc/prefix-align.s: New test.* testsuite/gas/ppc/ppc.exp: Run new test.2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>* configure.ac: Handle bpf-*-* targets.* configure.tgt (generic_target): Likewise.* configure: Regenerate.* Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c.(TARGET_CPU_HFILES): Add tc-bpf.h.* Makefile.in: Regenerated.* config/tc-bpf.c: New file.* config/tc-bpf.h: Likewise.* doc/Makefile.am (CPU_DOCS): Add c-bpf.texi.* doc/Makefile.in: Regenerated.* doc/all.texi: set BPF.* doc/as.texi: Add eBPF contents.* doc/c-bpf.texi: New file.* testsuite/gas/bpf/alu.d: New file.* testsuite/gas/bpf/mem-be.d: Likewise.* testsuite/gas/bpf/mem.s: Likewise.* testsuite/gas/bpf/mem.d: Likewise.* testsuite/gas/bpf/lddw-be.d: Likewise.* testsuite/gas/bpf/lddw.s: Likewise.* testsuite/gas/bpf/lddw.d: Likewise.* testsuite/gas/bpf/jump-be.d: Likewise.* testsuite/gas/bpf/jump.s: Likewise.* testsuite/gas/bpf/jump.d: Likewise.* testsuite/gas/bpf/exit-be.d: Likewise.* testsuite/gas/bpf/exit.s: Likewise.* testsuite/gas/bpf/exit.d: Likewise.* testsuite/gas/bpf/call-be.d: Likewise.* testsuite/gas/bpf/call.s: Likewise.* testsuite/gas/bpf/call.d: Likewise.* testsuite/gas/bpf/bpf.exp: Likewise.* testsuite/gas/bpf/atomic-be.d: Likewise.* testsuite/gas/bpf/atomic.s: Likewise.* testsuite/gas/bpf/atomic.d: Likewise.* testsuite/gas/bpf/alu-be.d: Likewise.* testsuite/gas/bpf/alu32-be.d: Likewise.* testsuite/gas/bpf/alu32.s: Likewise.* testsuite/gas/bpf/alu32.d: Likewise.* testsuite/gas/bpf/alu.s: Likewise.* testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF.* testsuite/gas/all/org-1.s: Support nop_type 6.* testsuite/gas/all/org-1.l: Updated to reflect changes inorg-1.s.2019-05-22 John Darrington <john@darrington.wattle.id.au>* config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update.(md_parse_option): new case OPTION_DOLLAR_HEX. (s12z_init_after_args):(<global>): Use s12z_strtol instead of strtol.* doc/c-s12z.texi (S12Z Options): Document new option -mdollar-hex.* testsuite/gas/s12z/dollar-hex.d: New file.* testsuite/gas/s12z/dollar-hex.s: New file.* testsuite/gas/s12z/s12z.exp: Add them.2019-05-21 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (parse_operands): Update case OP_RVC toparse p0 and P0.(do_vmrs): Add checks for valid operands with respect tocpu and fpu options.(do_vmsr): Likewise.(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NSand FPCXT_S.* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.* testsuite/gas/arm/vfp1xD_t2.d: Likewise.2019-05-21 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (TOGGLE_BIT): New.(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,csinv, csneg, cset, csetm and csel.(operand_parse_code): New OP_RR_ZR.(parse_operand): Handle case for OP_RR_ZR.(do_t_cond): New.(insns): New instructions for cinc, cinv, cneg, csinc,csinv, csneg, cset, csetm, csel.* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.* testsuite/gas/arm/armv8_1-m-cond.d: New test.* testsuite/gas/arm/armv8_1-m-cond.s: New test.2019-05-21 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (operand_parse_code): New entries forOP_RRnpcsp_I32 (register or integer operands).(do_mve_scalar_shift): New.(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshlsqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.* testsuite/gas/arm/mve-shift.d: New.* testsuite/gas/arm/mve-shift.s: New.* testsuite/gas/arm/mve-shift-bad.d: New.* testsuite/gas/arm/mve-shift-bad.s: New.* testsuite/gas/arm/mve-shift-bad.l: New.2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...* testsuite/gas/mips/r6-reg-constraints.s: this and add testcase for DAUI.* testsuite/gas/mips/r6-branch-constraints.l: Rename to ...* testsuite/gas/mips/r6-reg-constraints.l: this and add testfor DAUI.* testsuite/gas/mips/mips.exp: Rename test fromr6-branch-constraints to r6-reg-constraints.2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>PR 24559* config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVWreplacement.* testsuite/gas/arm/load-pseudo.s: New test input.* testsuite/gas/arm/m0-load-pseudo.d: New test.* testsuite/gas/arm/m23-load-pseudo.d: New test.* testsuite/gas/arm/m33-load-pseudo.d: New test.2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target namingconventions.* testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.* testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.* testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.* testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.* testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.* testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.* testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.2019-05-21 John Darrington <john@darrington.wattle.id.au>* expr.c (literal_prefix_dollar_hex): New variable.(operand)[case '$']: Use the new variable instead of the old macro.Also, move this instance of "case '$'" next to the other one, andenable it only in the complementary proprocessor case.* expr.h (literal_prefix_dollar_hex): Declare it.* config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex.* config/tc-ip2k.c: ditto* config/tc-mt.c: ditto* config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition.* config/tc-ip2k.h: ditto* config/tc-mt.h: ditto2019-05-20 Faraz Shahbazker <fshahbazker@wavecomp.com>PR 14798* config/tc-mips.c (s_mips_globl): Only treat symbols that arenot explicitly labelled as BSF_OBJECTs for IRIX targets.* testsuite/gas/mips/pr14798.s: New test source.* testsuite/gas/mips/pr14798-irix.d: New test.* testsuite/gas/mips/pr14798.d: Likewise.* testsuite/gas/mips/mips.exp: Run the new tests.2019-05-17 John Darrington <john@darrington.wattle.id.au>* doc/c-arm.texi (ARM Options): Remove "(r)" and "(tm)"* doc/c-bfin.texi (Blackfin Syntax): Remove "(r)"2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (check_simd_pred_availability): Refactor.(do_neon_dyadic_i_su): Refactor use of check_simd_pred_availability.(do_neon_dyadic_i64_su): Likewise.(do_neon_shl): Likewise.(do_neon_qshl): Likewise.(do_neon_rshl): Likewise.(do_neon_logic): Likewise.(do_neon_dyadic_if_su): Likewise.(do_neon_addsub_if_i): Likewise.(do_neon_mac_maybe_scalar): Likewise.(do_neon_fmac): Likewise.(do_neon_mul): Likewise.(do_neon_qdmulh): Likewise.(do_neon_qrdmlah): Likewise.(do_neon_abs_neg): Likewise.(do_neon_sli): Likewise.(do_neon_sri): Likewise.(do_neon_qshlu_imm): Likewise.(do_neon_cvt_1): Likewise.(do_neon_cvttb_1): Likewise.(do_neon_mvn): Likewise.(do_neon_rev): Likewise.(do_neon_dup): Likewise.(do_neon_mov): Likewise.(do_neon_rshift_round_imm): Likewise.(do_neon_sat_abs_neg): Likewise.(do_neon_cls): Likewise.(do_neon_clz): Likewise.(do_vmaxnm): Likewise.(do_vrint_1): Likewise.(do_vcmla): Likewise.(do_vcadd): Likewise.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* NEWS: Mention Armv8.1-M Mainline and MVE.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* testsuite/gas/arm/mve-tailpredloop.d: New test.* testsuite/gas/arm/mve-tailpredloop.s: New test.* testsuite/gas/arm/mve-vabav.d: New test.* testsuite/gas/arm/mve-vabav.s: New test.* testsuite/gas/arm/mve-vabd.d: New test.* testsuite/gas/arm/mve-vabd.s: New test.* testsuite/gas/arm/mve-vabsneg.d: New test.* testsuite/gas/arm/mve-vabsneg.s: New test.* testsuite/gas/arm/mve-vadc.d: New test.* testsuite/gas/arm/mve-vadc.s: New test.* testsuite/gas/arm/mve-vaddlv.d: New test.* testsuite/gas/arm/mve-vaddlv.s: New test.* testsuite/gas/arm/mve-vaddsub.d: New test.* testsuite/gas/arm/mve-vaddsub.s: New test.* testsuite/gas/arm/mve-vaddv.d: New test.* testsuite/gas/arm/mve-vaddv.s: New test.* testsuite/gas/arm/mve-vand.d: New test.* testsuite/gas/arm/mve-vand.s: New test.* testsuite/gas/arm/mve-vbic.d: New test.* testsuite/gas/arm/mve-vbic.s: New test.* testsuite/gas/arm/mve-vbrsr.d: New test.* testsuite/gas/arm/mve-vbrsr.s: New test.* testsuite/gas/arm/mve-vcadd.d: New test.* testsuite/gas/arm/mve-vcadd.s: New test.* testsuite/gas/arm/mve-vcls.d: New test.* testsuite/gas/arm/mve-vcls.s: New test.* testsuite/gas/arm/mve-vclz.d: New test.* testsuite/gas/arm/mve-vclz.s: New test.* testsuite/gas/arm/mve-vcmla.d: New test.* testsuite/gas/arm/mve-vcmla.s: New test.* testsuite/gas/arm/mve-vcmp.d: New test.* testsuite/gas/arm/mve-vcmp.s: New test.* testsuite/gas/arm/mve-vcmul.d: New test.* testsuite/gas/arm/mve-vcmul.s: New test.* testsuite/gas/arm/mve-vcvt-1.d: New test.* testsuite/gas/arm/mve-vcvt-1.s: New test.* testsuite/gas/arm/mve-vcvt-2.d: New test.* testsuite/gas/arm/mve-vcvt-2.s: New test.* testsuite/gas/arm/mve-vcvt-3.d: New test.* testsuite/gas/arm/mve-vcvt-3.s: New test.* testsuite/gas/arm/mve-vcvt-4.d: New test.* testsuite/gas/arm/mve-vcvt-4.s: New test.* testsuite/gas/arm/mve-vddup.d: New test.* testsuite/gas/arm/mve-vddup.s: New test.* testsuite/gas/arm/mve-vdup.d: New test.* testsuite/gas/arm/mve-vdup.s: New test.* testsuite/gas/arm/mve-veor.d: New test.* testsuite/gas/arm/mve-veor.s: New test.* testsuite/gas/arm/mve-vfma-vfms.d: New test.* testsuite/gas/arm/mve-vfma-vfms.s: New test.* testsuite/gas/arm/mve-vfmas.d: New test.* testsuite/gas/arm/mve-vfmas.s: New test.* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test.* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test.* testsuite/gas/arm/mve-vhcadd.d: New test.* testsuite/gas/arm/mve-vhcadd.s: New test.* testsuite/gas/arm/mve-vmax-vmin.d: New test.* testsuite/gas/arm/mve-vmax-vmin.s: New test.* testsuite/gas/arm/mve-vmaxa-vmina.d: New test.* testsuite/gas/arm/mve-vmaxa-vmina.s: New test.* testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test.* testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test.* testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test.* testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test.* testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test.* testsuite/gas/arm/mve-vmaxv-vminv.d: New test.* testsuite/gas/arm/mve-vmaxv-vminv.s: New test.* testsuite/gas/arm/mve-vmla.d: New test.* testsuite/gas/arm/mve-vmla.s: New test.* testsuite/gas/arm/mve-vmladav.d: New test.* testsuite/gas/arm/mve-vmladav.s: New test.* testsuite/gas/arm/mve-vmlaldav.d: New test.* testsuite/gas/arm/mve-vmlaldav.s: New test.* testsuite/gas/arm/mve-vmlalv.d: New test.* testsuite/gas/arm/mve-vmlalv.s: New test.* testsuite/gas/arm/mve-vmlas.d: New test.* testsuite/gas/arm/mve-vmlas.s: New test.* testsuite/gas/arm/mve-vmlav.d: New test.* testsuite/gas/arm/mve-vmlav.s: New test.* testsuite/gas/arm/mve-vmlsdav.d: New test.* testsuite/gas/arm/mve-vmlsdav.s: New test.* testsuite/gas/arm/mve-vmlsldav.d: New test.* testsuite/gas/arm/mve-vmlsldav.s: New test.* testsuite/gas/arm/mve-vmov-1.d: New test.* testsuite/gas/arm/mve-vmov-1.s: New test.* testsuite/gas/arm/mve-vmov-2.d: New test.* testsuite/gas/arm/mve-vmov-2.s: New test.* testsuite/gas/arm/mve-vmul.d: New test.* testsuite/gas/arm/mve-vmul.s: New test.* testsuite/gas/arm/mve-vmulh.d: New test.* testsuite/gas/arm/mve-vmulh.s: New test.* testsuite/gas/arm/mve-vmullbt.d: New test.* testsuite/gas/arm/mve-vmullbt.s: New test.* testsuite/gas/arm/mve-vmvn.d: New test.* testsuite/gas/arm/mve-vmvn.s: New test.* testsuite/gas/arm/mve-vorn.d: New test.* testsuite/gas/arm/mve-vorn.s: New test.* testsuite/gas/arm/mve-vorr.d: New test.* testsuite/gas/arm/mve-vorr.s: New test.* testsuite/gas/arm/mve-vpnot.d: New test.* testsuite/gas/arm/mve-vpnot.s: New test.* testsuite/gas/arm/mve-vpsel.d: New test.* testsuite/gas/arm/mve-vpsel.s: New test.* testsuite/gas/arm/mve-vpt.d: New test.* testsuite/gas/arm/mve-vpt.s: New test.* testsuite/gas/arm/mve-vqabsneg.s: New test.* testsuite/gas/arm/mve-vqaddsub.d: New test.* testsuite/gas/arm/mve-vqaddsub.s: New test.* testsuite/gas/arm/mve-vqdmladh.d: New test.* testsuite/gas/arm/mve-vqdmladh.s: New test.* testsuite/gas/arm/mve-vqdmlah.d: New test.* testsuite/gas/arm/mve-vqdmlah.s: New test.* testsuite/gas/arm/mve-vqdmlash.d: New test.* testsuite/gas/arm/mve-vqdmlash.s: New test.* testsuite/gas/arm/mve-vqdmlsdh.d: New test.* testsuite/gas/arm/mve-vqdmlsdh.s: New test.* testsuite/gas/arm/mve-vqdmulh.d: New test.* testsuite/gas/arm/mve-vqdmulh.s: New test.* testsuite/gas/arm/mve-vqdmull.d: New test.* testsuite/gas/arm/mve-vqdmull.s: New test.* testsuite/gas/arm/mve-vqmovn.d: New test.* testsuite/gas/arm/mve-vqmovn.s: New test.* testsuite/gas/arm/mve-vqrshl.d: New test.* testsuite/gas/arm/mve-vqrshl.s: New test.* testsuite/gas/arm/mve-vqrshrn.d: New test.* testsuite/gas/arm/mve-vqrshrn.s: New test.* testsuite/gas/arm/mve-vqshl.d: New test.* testsuite/gas/arm/mve-vqshl.s: New test.* testsuite/gas/arm/mve-vrev.d: New test.* testsuite/gas/arm/mve-vrev.s: New test.* testsuite/gas/arm/mve-vrint.d: New test.* testsuite/gas/arm/mve-vrint.s: New test.* testsuite/gas/arm/mve-vrmlaldavh.d: New test.* testsuite/gas/arm/mve-vrmlaldavh.s: New test.* testsuite/gas/arm/mve-vrshl.d: New test.* testsuite/gas/arm/mve-vrshl.s: New test.* testsuite/gas/arm/mve-vsbc.d: New test.* testsuite/gas/arm/mve-vsbc.s: New test.* testsuite/gas/arm/mve-vshl.d: New test.* testsuite/gas/arm/mve-vshl.s: New test.* testsuite/gas/arm/mve-vshlc.d: New test.* testsuite/gas/arm/mve-vshlc.s: New test.* testsuite/gas/arm/mve-vshll.d: New test.* testsuite/gas/arm/mve-vshll.s: New test.* testsuite/gas/arm/mve-vshr.d: New test.* testsuite/gas/arm/mve-vshr.s: New test.* testsuite/gas/arm/mve-vshrn.d: New test.* testsuite/gas/arm/mve-vshrn.s: New test.* testsuite/gas/arm/mve-vsli.d: New test.* testsuite/gas/arm/mve-vsli.s: New test.* testsuite/gas/arm/mve-vsri.d: New test.* testsuite/gas/arm/mve-vsri.s: New test.* testsuite/gas/arm/mve-vstld.d: New test.* testsuite/gas/arm/mve-vstld.s: New test.* testsuite/gas/arm/mve-vstrldr-1.d: New test.* testsuite/gas/arm/mve-vstrldr-1.s: New test.* testsuite/gas/arm/mve-vstrldr-2.d: New test.* testsuite/gas/arm/mve-vstrldr-2.s: New test.* testsuite/gas/arm/mve-vstrldr-3.d: New test.* testsuite/gas/arm/mve-vstrldr-3.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (T16_32_TAB): Add new instructions.(do_t_loloop): Changed to handle tail predication variants.(md_apply_fix): Likewise.(insns): Add entries for MVE mnemonics.* testsuite/gas/arm/mve-tailpredloop-bad.d: New test.* testsuite/gas/arm/mve-tailpredloop-bad.l: New test.* testsuite/gas/arm/mve-tailpredloop-bad.s: New test.* testsuite/gas/arm/mve-tailpredloop.d: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_mve_vshll): New encoding function.(do_mve_vshlc): Likewise.(insns): Add entries for MVE mnemonics.* testsuite/gas/arm/mve-vshlc-bad.d: New test.* testsuite/gas/arm/mve-vshlc-bad.l: New test.* testsuite/gas/arm/mve-vshlc-bad.s: New test.* testsuite/gas/arm/mve-vshll-bad.d: New test.* testsuite/gas/arm/mve-vshll-bad.l: New test.* testsuite/gas/arm/mve-vshll-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): Add new operand.(parse_operands): Handle new operand.(do_neon_shl_imm): Accept MVE variants.(do_neon_shl): Likewise.(do_neon_qshl_imm): Likewise.(do_neon_qshl): Likewise.(do_neon_qshlu_imm): Likewise.(insns): Likewise.* testsuite/gas/arm/mve-vqshl-bad.d: New test.* testsuite/gas/arm/mve-vqshl-bad.l: New test.* testsuite/gas/arm/mve-vqshl-bad.s: New test.* testsuite/gas/arm/mve-vshl-bad.d: New test.* testsuite/gas/arm/mve-vshl-bad.l: New test.* testsuite/gas/arm/mve-vshl-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_neon_sli): Accept MVE variants.(do_neon_sri): Likewise.(do_neon_rev): Likewise.(do_neon_rshift_round_imm): Likewise.(insns): Likewise.* testsuite/gas/arm/mve-vrev-bad.d: New test.* testsuite/gas/arm/mve-vrev-bad.l: New test.* testsuite/gas/arm/mve-vrev-bad.s: New test.* testsuite/gas/arm/mve-vshr-bad.d: New test.* testsuite/gas/arm/mve-vshr-bad.l: New test.* testsuite/gas/arm/mve-vshr-bad.s: New test.* testsuite/gas/arm/mve-vsli-bad.d: New test.* testsuite/gas/arm/mve-vsli-bad.l: New test.* testsuite/gas/arm/mve-vsli-bad.s: New test.* testsuite/gas/arm/mve-vsri-bad.d: New test.* testsuite/gas/arm/mve-vsri-bad.l: New test.* testsuite/gas/arm/mve-vsri-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_vrint_1): Accept MVE variants.(insns): Change entries to accept MVE variants.* testsuite/gas/arm/mve-vrint-bad.d: New test.* testsuite/gas/arm/mve-vrint-bad.l: New test.* testsuite/gas/arm/mve-vrint-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt,M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb,M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt,M_MNEM_vqrshrunb): New instruction encodings.(do_mve_vshrn): New encoding function.(insns): Add entries for MVE mnemonics.* testsuite/gas/arm/mve-vqrshrn-bad.d: New test.* testsuite/gas/arm/mve-vqrshrn-bad.l: New test.* testsuite/gas/arm/mve-vqrshrn-bad.s: New test.* testsuite/gas/arm/mve-vshrn-bad.d: New test.* testsuite/gas/arm/mve-vshrn-bad.l: New test.* testsuite/gas/arm/mve-vshrn-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb,M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings.(do_mve_vqmovn): New encoding function.(do_neon_rshl): Change to accepte MVE variants.(insns): Change entries and add new for MVE mnemonics.* testsuite/gas/arm/mve-vqmovn-bad.d: New test.* testsuite/gas/arm/mve-vqmovn-bad.l: New test.* testsuite/gas/arm/mve-vqmovn-bad.s: New test.* testsuite/gas/arm/mve-vqrshl-bad.d: New test.* testsuite/gas/arm/mve-vqrshl-bad.l: New test.* testsuite/gas/arm/mve-vqrshl-bad.s: New test.* testsuite/gas/arm/mve-vrshl-bad.d: New test.* testsuite/gas/arm/mve-vrshl-bad.l: New test.* testsuite/gas/arm/mve-vrshl-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): Add new operand.(parse_operands): Handle new operand.(do_mve_vqdmull): New encoding function.(insns): Add entry for MVE mnemonics.* testsuite/gas/arm/mve-vqdmull-bad.d: New test.* testsuite/gas/arm/mve-vqdmull-bad.l: New test.* testsuite/gas/arm/mve-vqdmull-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): Add new operand.(parse_operands): Handle new operand.(mve_encode_qqr): Handle new instructions.(do_neon_qdmulh): Add support for MVE variants.(do_neon_qrdmlah): Likewise.(do_mve_vqdmlah): New encoding function.(insns): Change entries and add new entries for MVE mnemonics.* testsuite/gas/arm/mve-vqdmulh-bad.d: New test.* testsuite/gas/arm/mve-vqdmulh-bad.l: New test.* testsuite/gas/arm/mve-vqdmulh-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_mve_vqdmladh): New encoding function.(insns): Add entries for MVE mnemonics.* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_mve_vpsel): New encoding function.(do_mve_vpnot): Likewise.(insns): Add entries for MVE mnemonics.* testsuite/gas/arm/mve-vpnot-bad.d: New test.* testsuite/gas/arm/mve-vpnot-bad.l: New test.* testsuite/gas/arm/mve-vpnot-bad.s: New test.* testsuite/gas/arm/mve-vpsel-bad.d: New test.* testsuite/gas/arm/mve-vpsel-bad.l: New test.* testsuite/gas/arm/mve-vpsel-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_neon_mvn): Change to accept MVE variants.(do_neon_sat_abs_neg): Likewise.(insns): Likewise.* testsuite/gas/arm/mve-vmvn-bad.d: New test.* testsuite/gas/arm/mve-vmvn-bad.l: New test.* testsuite/gas/arm/mve-vmvn-bad.s: New test.* testsuite/gas/arm/mve-vqabsneg-bad.d: New test.* testsuite/gas/arm/mve-vqabsneg-bad.l: New test.* testsuite/gas/arm/mve-vqabsneg-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_mve_vmlas): New encoding function.(do_mve_vmulh): Likewise.(insns): Add entries for MVE mnemonics.* testsuite/gas/arm/mve-vmlas-bad.d: New test.* testsuite/gas/arm/mve-vmlas-bad.l: New test.* testsuite/gas/arm/mve-vmlas-bad.s: New test.* testsuite/gas/arm/mve-vmulh-bad.d: New test.* testsuite/gas/arm/mve-vmulh-bad.l: New test.* testsuite/gas/arm/mve-vmulh-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): New operand.(parse_operands): Handle new operand.(mve_encode_qqr): Handle new instructions.(do_neon_dyadic_i64_su): Accept MVE variants.(neon_dyadic_misc): Likewise.(do_neon_mac_maybe_scalar): Likewise.(do_neon_mul): Likewise.(insns): Change to accept MVE variants.* testsuite/gas/arm/mve-vmla-bad.d: New test.* testsuite/gas/arm/mve-vmla-bad.l: New test.* testsuite/gas/arm/mve-vmla-bad.s: New test.* testsuite/gas/arm/mve-vmul-bad-1.d: New test.* testsuite/gas/arm/mve-vmul-bad-1.l: New test.* testsuite/gas/arm/mve-vmul-bad-1.s: New test.* testsuite/gas/arm/mve-vmul-bad-2.d: New test.* testsuite/gas/arm/mve-vmul-bad-2.l: New test.* testsuite/gas/arm/mve-vmul-bad-2.s: New test.* testsuite/gas/arm/mve-vqaddsub-bad.d: New test.* testsuite/gas/arm/mve-vqaddsub-bad.l: New test.* testsuite/gas/arm/mve-vqaddsub-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (M_MNEM_vmlaldav, M_MNEM_vmlaldava,M_MNEM_vmlaldavx, M_MNEM_vmlaldavax, M_MNEM_vmlsldav,M_MNEM_vmlsldava, M_MNEM_vmlsldavx, M_MNEM_vmlsldavax,M_MNEM_vrmlaldavhx, M_MNEM_vrmlaldavhax, M_MNEM_vrmlsldavh,M_MNEM_vrmlsldavha, M_MNEM_vrmlsldavhx, M_MNEM_vrmlsldavhax): Newinstruction encodings.(NEON_SHAPE_DEF): New shape(mve_encode_rrqq): New encoding helper function.(do_mve_vmlaldav): New encoding function.(do_mve_vrmlaldavh): New encoding function.(insns): Add entries for MVE mnemonics.* testsuite/gas/arm/mve-vmlaldav-bad.d: New test.* testsuite/gas/arm/mve-vmlaldav-bad.l: New test.* testsuite/gas/arm/mve-vmlaldav-bad.s: New test.* testsuite/gas/arm/mve-vmlalv-bad.d: New test.* testsuite/gas/arm/mve-vmlalv-bad.l: New test.* testsuite/gas/arm/mve-vmlalv-bad.s: New test.* testsuite/gas/arm/mve-vmlsldav-bad.d: New test.* testsuite/gas/arm/mve-vmlsldav-bad.l: New test.* testsuite/gas/arm/mve-vmlsldav-bad.s: New test.* testsuite/gas/arm/mve-vrmlaldavh-bad.d: New test.* testsuite/gas/arm/mve-vrmlaldavh-bad.l: New test.* testsuite/gas/arm/mve-vrmlaldavh-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv,M_MNEM_vminav): New instruction encodings.(do_mve_vmaxv): New encoding function.(insns): Add entries for new MVE mnemonics.* testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test.* testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test.* testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.(insns): Add entries for new mnemonics.* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test.* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test.* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function.(do_mve_vmaxnma_vminnma): Likewise.(do_neon_dyadic_if_su): Change to support MVE variants.(do_vmaxnm): Likewise.(insns): Change to accept MVE variants and add new.* testsuite/gas/arm/mve-vmax-vmin-bad.d: New test.* testsuite/gas/arm/mve-vmax-vmin-bad.l: New test.* testsuite/gas/arm/mve-vmax-vmin-bad.s: New test.* testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test.* testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test.* testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test.* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test.* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test.* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test.* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test.* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test.* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): New operand.(parse_operands): Handle new operand.(mve_encode_qqr): Change to support new instructions.(enum vfp_or_neon_is_neon_bits): Moved.(vfp_or_neon_is_neon): Moved.(check_simd_pred_availability): Moved.(do_neon_dyadic_i_su): Changed to support MVE variants.(neon_dyadic_misc): Changed mve_encode_qqr call.(do_mve_vbrsr): Likewise.(do_mve_vhcadd): New encoding function.(insns): Change existing to accept MVE variants and add new.* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test.* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test.* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test.* testsuite/gas/arm/mve-vhcadd-bad.d: New test.* testsuite/gas/arm/mve-vhcadd-bad.l: New test.* testsuite/gas/arm/mve-vhcadd-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_neon_fmac): Change to support MVE variants.(insns): Change to accept MVE variants.* testsuite/gas/arm/mve-vfma-vfms-bad.d: New test.* testsuite/gas/arm/mve-vfma-vfms-bad.l: New test.* testsuite/gas/arm/mve-vfma-vfms-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup,M_MNEM_viwdup): New instruction encodings.(NEON_SHAPE_DEF): New shapes.(do_mve_viddup): New encoding function.(do_neon_dup): Change to support new MVE variants.(insns): Change existing to accept MVE variants and add new.* testsuite/gas/arm/mve-vddup-bad.d: New test.* testsuite/gas/arm/mve-vddup-bad.l: New test.* testsuite/gas/arm/mve-vddup-bad.s: New test.* testsuite/gas/arm/mve-vdup-bad.d: New test.* testsuite/gas/arm/mve-vdup-bad.l: New test.* testsuite/gas/arm/mve-vdup-bad.s: New test.* testsuite/gas/arm/mve-vidup-bad.d: New test.* testsuite/gas/arm/mve-vidup-bad.l: New test.* testsuite/gas/arm/mve-vidup-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_mve_vfmas): New encoding function.(do_neon_cls): Change to support MVE variants.(do_neon_clz): Change to support MVE variants.(insns): Change to support MVE variants and add new.* testsuite/gas/arm/mve-vcls-bad.d: New test.* testsuite/gas/arm/mve-vcls-bad.l: New test.* testsuite/gas/arm/mve-vcls-bad.s: New test.* testsuite/gas/arm/mve-vclz-bad.d: New test.* testsuite/gas/arm/mve-vclz-bad.l: New test.* testsuite/gas/arm/mve-vclz-bad.s: New test.* testsuite/gas/arm/mve-vfmas-bad.d: New test.* testsuite/gas/arm/mve-vfmas-bad.l: New test.* testsuite/gas/arm/mve-vfmas-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): New operands.(parse_operands): Handle new operands.(do_mve_vcmul): New encoding function.(do_vcmla): Change to support MVE variants.(do_vcadd): Change to support MVE variants.(insns): Change existing to support MVE variants and add new.* testsuite/gas/arm/mve-vcadd-bad-1.d: New test.* testsuite/gas/arm/mve-vcadd-bad-1.l: New test.* testsuite/gas/arm/mve-vcadd-bad-1.s: New test.* testsuite/gas/arm/mve-vcadd-bad-2.d: New test.* testsuite/gas/arm/mve-vcadd-bad-2.l: New test.* testsuite/gas/arm/mve-vcadd-bad-2.s: New test.* testsuite/gas/arm/mve-vcmla-bad-1.d: New test.* testsuite/gas/arm/mve-vcmla-bad-1.l: New test.* testsuite/gas/arm/mve-vcmla-bad-1.s: New test.* testsuite/gas/arm/mve-vcmla-bad-2.d: New test.* testsuite/gas/arm/mve-vcmla-bad-2.l: New test.* testsuite/gas/arm/mve-vcmla-bad-2.s: New test.* testsuite/gas/arm/mve-vcmul-bad-1.d: New test.* testsuite/gas/arm/mve-vcmul-bad-1.l: New test.* testsuite/gas/arm/mve-vcmul-bad-1.s: New test.* testsuite/gas/arm/mve-vcmul-bad-2.d: New test.* testsuite/gas/arm/mve-vcmul-bad-2.l: New test.* testsuite/gas/arm/mve-vcmul-bad-2.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): New operands.(parse_operands): Handle new operands.(enum vfp_or_neon_is_neon_bits): Moved(vfp_or_neon_is_neon): Moved(check_simd_pred_availability): Moved.(do_neon_logic): Change to accept MVE variants.(insns): Changed to accept MVE variants.* testsuite/gas/arm/mve-vand-bad.d: New test.* testsuite/gas/arm/mve-vand-bad.l: New test.* testsuite/gas/arm/mve-vand-bad.s: New test.* testsuite/gas/arm/mve-vbic-bad.d: New test.* testsuite/gas/arm/mve-vbic-bad.l: New test.* testsuite/gas/arm/mve-vbic-bad.s: New test.* testsuite/gas/arm/mve-veor-bad.d: New test.* testsuite/gas/arm/mve-veor-bad.l: New test.* testsuite/gas/arm/mve-veor-bad.s: New test.* testsuite/gas/arm/mve-vorn-bad.d: New test.* testsuite/gas/arm/mve-vorn-bad.l: New test.* testsuite/gas/arm/mve-vorn-bad.s: New test.* testsuite/gas/arm/mve-vorr-bad.d: New test.* testsuite/gas/arm/mve-vorr-bad.l: New test.* testsuite/gas/arm/mve-vorr-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv,M_MNEM_vaddva): New instruction encodings.(mve_encode_rq): New encoding helper function.(do_mve_vaddlv): New encoding function.(do_mve_vaddv): New encoding function.* testsuite/gas/arm/mve-vaddlv-bad.d: New test.* testsuite/gas/arm/mve-vaddlv-bad.l: New test.* testsuite/gas/arm/mve-vaddlv-bad.s: New test.* testsuite/gas/arm/mve-vaddv-bad.d: New test.* testsuite/gas/arm/mve-vaddv-bad.l: New test.* testsuite/gas/arm/mve-vaddv-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):New instruction encodings.(do_mve_vadc): New encoding instruction.(do_mve_vbrsr): Likewise.(do_mve_vsbc): Likewise.* testsuite/gas/arm/mve-vadc-bad.d: New test.* testsuite/gas/arm/mve-vadc-bad.l: New test.* testsuite/gas/arm/mve-vadc-bad.s: New test.* testsuite/gas/arm/mve-vbrsr-bad.d: New test.* testsuite/gas/arm/mve-vbrsr-bad.l: New test.* testsuite/gas/arm/mve-vbrsr-bad.s: New test.* testsuite/gas/arm/mve-vsbc-bad.d: New test.* testsuite/gas/arm/mve-vsbc-bad.l: New test.* testsuite/gas/arm/mve-vsbc-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (MVE_BAD_QREG): New error message.(enum operand_parse_code): Define new operand.(parse_operands): Handle new operand.(do_mve_vpt): Change for VPT blocks.(NEON_SHAPE_DEF): New shape.(neon_logbits): Moved.(LOW4): Moved(HI1): Moved(mve_get_vcmp_vpt_cond): New function to translate vpt conditions.(do_mve_vcmp): New encoding function.(do_vfp_nsyn_cmp): Changed to support MVE variants.(insns): Change to support MVE variants of vcmp and add vpt.* testsuite/gas/arm/mve-vcmp-bad-1.d: New test.* testsuite/gas/arm/mve-vcmp-bad-1.l: New test.* testsuite/gas/arm/mve-vcmp-bad-1.s: New test.* testsuite/gas/arm/mve-vcmp-bad-2.d: New test.* testsuite/gas/arm/mve-vcmp-bad-2.l: New test.* testsuite/gas/arm/mve-vcmp-bad-2.s: New test.* testsuite/gas/arm/mve-vpt-bad-1.d: New test.* testsuite/gas/arm/mve-vpt-bad-1.l: New test.* testsuite/gas/arm/mve-vpt-bad-1.s: New test.* testsuite/gas/arm/mve-vpt-bad-2.d: New test.* testsuite/gas/arm/mve-vpt-bad-2.l: New test.* testsuite/gas/arm/mve-vpt-bad-2.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (struct arm_it): Expand isscalar field to be able todistinguish between types of scalar.(parse_typed_reg_or_scalar): Change to accept MVE scalar variants.(parse_scalar): Likewise.(parse_neon_mov): Accept MVE variant.(po_scalar_or_goto): Make use reg_type.(parse_operands): Change uses of po_scalar_or_goto.(do_vfp_sp_monadic): Change to accept MVE variants.(do_vfp_reg_from_sp): Likewise.(do_vfp_sp_from_reg): Likewise.(do_vfp_dp_rd_rm): Likewise.(do_vfp_dp_rd_rn_rm): Likewise.(do_vfp_dp_rm_rd_rn): Likewise.(M_MNEM_vmovlt, M_MNEM_vmovlb, M_MNEM_vmovnt, M_MNEM_vmovnb): Newinstruction encodings.(NEON_SHAPE_DEF): New shape.(do_mve_mov): New encoding fuction.(do_mve_movn): Likewise.(do_mve_movl): Likewise.(do_neon_mov): Change to accept MVE variants.(mcCE): New MACRO.(insns): Accept new MVE variants and instructions.* testsuite/gas/arm/mve-vmov-bad-1.d: New test.* testsuite/gas/arm/mve-vmov-bad-1.l: New test.* testsuite/gas/arm/mve-vmov-bad-1.s: New test.* testsuite/gas/arm/mve-vmov-bad-2.d: New test.* testsuite/gas/arm/mve-vmov-bad-2.l: New test.* testsuite/gas/arm/mve-vmov-bad-2.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum operand_parse_code): Add new operand.(parse_operands): Handle new operand.(do_neon_cvt_1): Handle MVE variants.(do_neon_cvttb_1): Likewise.(insns): Accept MVE variants.* testsuite/gas/arm/mve-vcvt-bad-1.d: New test.* testsuite/gas/arm/mve-vcvt-bad-1.l: New test.* testsuite/gas/arm/mve-vcvt-bad-1.s: New test.* testsuite/gas/arm/mve-vcvt-bad-2.d: New test.* testsuite/gas/arm/mve-vcvt-bad-2.l: New test.* testsuite/gas/arm/mve-vcvt-bad-2.s: New test.* testsuite/gas/arm/mve-vcvt-bad-3.d: New test.* testsuite/gas/arm/mve-vcvt-bad-3.l: New test.* testsuite/gas/arm/mve-vcvt-bad-3.s: New test.* testsuite/gas/arm/mve-vcvt-bad-4.d: New test.* testsuite/gas/arm/mve-vcvt-bad-4.l: New test.* testsuite/gas/arm/mve-vcvt-bad-4.s: New test.* testsuite/gas/arm/mve-vcvt-bad.d: New test.* testsuite/gas/arm/mve-vcvt-bad.l: New test.* testsuite/gas/arm/mve-vcvt-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (struct arm_it): Make immisreg field larger to holdtype of register.(enum shift_kind): Add SHIFT_UXTW shift kind.(enum parse_shift_mode): Add SHIFT_UXTW_IMMEDIATE shift mode.(parse_shift): Handle new shift type.(parse_address_main): Accept new addressing modes.(M_MNEM_vstrb, M_MNEM_vstrh, M_MNEM_vstrw, M_MNEM_vstrd,M_MNEM_vldrb, M_MNEM_vldrh, M_MNEM_vldrw, M_MNEM_vldrd): Newinstruction encodings.(do_mve_vstr_vldr_QI): New encoding functions.(do_mve_vstr_vldr_RQ): Likewise.(do_mve_vstr_vldr_RI): Likewise.(do_mve_vstr_vldr): Likewise.* testsuite/gas/arm/mve-vldr-bad-1.d: New test.* testsuite/gas/arm/mve-vldr-bad-1.l: New test.* testsuite/gas/arm/mve-vldr-bad-1.s: New test.* testsuite/gas/arm/mve-vldr-bad-2.d: New test.* testsuite/gas/arm/mve-vldr-bad-2.l: New test.* testsuite/gas/arm/mve-vldr-bad-2.s: New test.* testsuite/gas/arm/mve-vldr-bad-3.d: New test.* testsuite/gas/arm/mve-vldr-bad-3.l: New test.* testsuite/gas/arm/mve-vldr-bad-3.s: New test.* testsuite/gas/arm/mve-vstr-bad-1.d: New test.* testsuite/gas/arm/mve-vstr-bad-1.l: New test.* testsuite/gas/arm/mve-vstr-bad-1.s: New test.* testsuite/gas/arm/mve-vstr-bad-2.d: New test.* testsuite/gas/arm/mve-vstr-bad-2.l: New test.* testsuite/gas/arm/mve-vstr-bad-2.s: New test.* testsuite/gas/arm/mve-vstr-bad-3.d: New test.* testsuite/gas/arm/mve-vstr-bad-3.l: New test.* testsuite/gas/arm/mve-vstr-bad-3.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum it_instruction_type): Add MVE_UNPREDICABLE_INSN.(BAD_EL_TYPE): New error message.(parse_neon_el_struct_list): Adapt to be able to accept MVE variant.(parse_address_main): Likewise.(group_reloc_type): Add GROUP_MVE.(enum operand_parse_code): Add new operands.(parse_operands): Handle new operands.(M_MNEM_vst20, M_MNEM_vst21, M_MNEM_vst40, M_MNEM_vst41, M_MNEM_vst42,M_MNEM_vst43, M_MNEM_vld20, M_MNEM_vld21, M_MNEM_vld40, M_MNEM_vld41,M_MNEM_vld42, M_MNEM_vld43): New encodings.(do_mve_vst_vld): New encoding function.(do_neon_ld_st_interleave): Use BAD_EL_TYPE.(it_fsm_pre_encode): Handle new it_instruction_type(handle_pred_state): Likewise.* testsuite/gas/arm/mve-vstld-bad.d: New test.* testsuite/gas/arm/mve-vstld-bad.l: New test.* testsuite/gas/arm/mve-vstld-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (BAD_MVE_AUTO): New error message.(BAD_MVE_SRCDEST): Likewise.(mark_feature_used): Diagnose MVE only instructions when inauto-detection mode or -march=all.(enum operand_parse_code): Define new operand.(parse_operands): Handle new operand.(M_MNEM_vmullt, M_MNEM_vmullb): New encodings.(mve_encode_qqq): New encoding helper function.(do_mve_vmull): New encoding function.(insns): Handle new instructions.* testsuite/gas/arm/mve-vmullbt-bad.d: New test.* testsuite/gas/arm/mve-vmullbt-bad.l: New test.* testsuite/gas/arm/mve-vmullbt-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (struct asm_opcode): Make avalue a full int.(BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors.(enum operand_parse_code): Handle new operands.(parse_operands): Likewise.(M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx,M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx,M_MNEM_vmlsdavax): Define new encodings.(NEON_SHAPE_DEF): Add new shape.(neon_check_type): Use BAD_SIMD_TYPE.(mve_encode_rqq): New encoding helper function.(do_mve_vabav, do_mve_vmladav): New encoding functions.(mCEF): New MACRO.* testsuite/gas/arm/mve-vabav-bad.d: New test.* testsuite/gas/arm/mve-vabav-bad.l: New test.* testsuite/gas/arm/mve-vabav-bad.s: New test.* testsuite/gas/arm/mve-vmladav-bad.d: New test.* testsuite/gas/arm/mve-vmladav-bad.l: New test.* testsuite/gas/arm/mve-vmladav-bad.s: New test.* testsuite/gas/arm/mve-vmlav-bad.d: New test.* testsuite/gas/arm/mve-vmlav-bad.l: New test.* testsuite/gas/arm/mve-vmlav-bad.s: New test.* testsuite/gas/arm/mve-vmlsdav-bad.d: New test.* testsuite/gas/arm/mve-vmlsdav-bad.l: New test.* testsuite/gas/arm/mve-vmlsdav-bad.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.(insns): Change vabs and vneg entries to accept MVE variants.* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (enum it_instruction_type): Rename to...(enum pred_instruction_type): ... this. Include VPT types.(it_insn_type): Rename to ...(pred_insn_type): .. this.(arm_it): Change comment.(enum arm_reg_type): Add new value.(reg_expected_msgs): New entry.(asm_opcode): Add mayBeVecPred member.(BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT,MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS.(arm_vcond_hsh): New table for vector condition codes.(now_it): Rename to ...(now_pred): ... this.(now_it_compatible): Rename to ...(now_pred_compatible): ... this.(in_it_block): Rename to ...(in_pred_block): ... this.(handle_it_state): Rename to ...(handle_pred_state): ... this. And change it to accept VPT blocks.(set_it_insn_type): Rename to ...(set_pred_insn_type): ... this.(set_it_insn_type_nonvoid): Rename to ...(set_pred_insn_type_nonvoid): ... this.(set_it_insn_type_last): Rename to ...(set_pred_insn_type_last): ... this.(record_feature_use): Moved.(mark_feature_used): Likewise.(parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ.(emit_insn): Use renamed functions and variables.(enum operand_parse_code): Add new operands.(parse_operands): Handle new operands.(do_scalar_fp16_v82_encode): Change predication detection.(do_it): Use renamed functions and variables.(do_t_add_sub): Likewise.(do_t_arit3): Likewise.(do_t_arit3c): Likewise.(do_t_blx): Likewise.(do_t_branch): Likewise.(do_t_bkpt_hlt1): Likewise.(do_t_branch23): Likewise.(do_t_bx): Likewise.(do_t_bxj): Likewise.(do_t_cond): Likewise.(do_t_csdb): Likewise.(do_t_cps): Likewise.(do_t_cpsi): Likewise.(do_t_cbz): Likewise.(do_t_it): Likewise.(do_mve_vpt): New function to handle VPT blocks.(encode_thumb2_multi): Use renamed functions and variables.(do_t_ldst): Use renamed functions and variables.(do_t_mov_cmp): Likewise.(do_t_mvn_tst): Likewise.(do_t_mul): Likewise.(do_t_nop): Likewise.(do_t_neg): Likewise.(do_t_rsb): Likewise.(do_t_setend): Likewise.(do_t_shift): Likewise.(do_t_smc): Likewise.(do_t_tb): Likewise.(do_t_udf): Likewise.(do_t_loloop): Likewise.(do_neon_cvt_1): Likewise.(do_vfp_nsyn_cvt_fpv8): Likewise.(do_vsel): Likewise.(do_vmaxnm): Likewise.(do_vrint_1): Likewise.(do_crypto_2op_1): Likewise.(do_crypto_3op_1): Likewise.(do_crc32_1): Likewise.(it_fsm_pre_encode): Likewise.(it_fsm_post_encode): Likewise.(force_automatic_it_block_close): Likewise.(check_it_blocks_finished): Likewise.(check_pred_blocks_finished): Likewise.(arm_cleanup): Likewise.(now_it_add_mask): Rename to ...(now_pred_add_mask): ... this. And use new variables and functions.(NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl.(N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs.(neon_check_type): Generalize error message.(mve_encode_qqr): New MVE generic encoding function.(neon_dyadic_misc): Change to accept MVE variants.(do_neon_dyadic_if_su): Likewise.(do_neon_addsub_if_i): Likewise.(do_neon_dyadic_long): Likewise.(vfp_or_neon_is_neon): Add extra checks.(check_simd_pred_availability): Helper function to check SIMDinstruction availability with respect to predication.(enum opcode_tag): New suffix value.(opcode_lookup): Change to handle VPT blocks.(new_automatic_it_block): Rename to ...(close_automatic_it_block): ...this.(TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU,toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF,NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for newfield.(mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs.(insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVEvariants. Add entries for vscclrm, and vpst.(md_begin): Add arm_vcond_hsh initialization.* config/tc-arm.h (enum it_state): Rename to...(enum pred_state): ...this.(struct current_it): Rename to...(struct current_pred): ...this.(enum pred_type): New enum.(struct arm_segment_info_type): Use current_pred.* testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message.* testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message.* testsuite/gas/arm/dotprod-illegal.l: Update error message.* testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test.* testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test.* testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test.* testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test.* testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test.* testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test.* testsuite/gas/arm/mve-vpst-bad.d: New test.* testsuite/gas/arm/mve-vpst-bad.l: New test.* testsuite/gas/arm/mve-vpst-bad.s: New test.* testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (mve_ext, mve_fp_ext): New features.(armv8_1m_main_ext_table): Add new extensions.(aeabi_set_public_attributes): Translate new features to new build attributes.(arm_convert_symbolic_attribute): Add Tag_MVE_arch.* doc/c-arm.texi: Document new extensions and new build attribute.2019-05-15 John Darrington <john@darrington.wattle.id.au>* config/tc-s12z.c (register_prefix): New variable. (md_show_usage,md_parse_option): parse the new option.(lex_reg_name): Scan the prefix if one is set.* doc/c-s12z.texi (S12Z-Opts): Document the new option.* testsuite/gas/s12z/reg-prefix.d: New file.* testsuite/gas/s12z/reg-prefix.s: New file.* testsuite/gas/s12z/s12z.exp: Add them.2019-05-14 John Darrington <john@darrington.wattle.id.au>* doc/as.texi (Machine Dependencies): Fix misaligned menu entry.2019-05-15 Alan Modra <amodra@gmail.com>* config/tc-csky.c (md_convert_frag): Initialise trailingpadding for COND_JUMP_PIC.2019-05-15 Alan Modra <amodra@gmail.com>* dwarf2dbg.c: Whitespace fixes.(get_filenum): Don't strdup "file". Adjust error message.(dwarf2_directive_filename): Use an unsigned type for "num".Catch truncation of file number and overflow of get_filenumXRESIZEVEC multiplication. Delete dead code.2019-05-15 Alan Modra <amodra@gmail.com>PR 24538* config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of linechars in setting endp.2019-05-14 Nick Clifton <nickc@redhat.com>PR 24538* config/tc-i386-intel.c (i386_intel_simplify_register): Rejectillegal register numbers.2019-05-10 Nick Clifton <nickc@redhat.com>PR 24538* macro.c (get_any_string): Increase size of buffer used to holddecimal value of expression result.* dw2gencfi.c (get_debugseg_name): Handle an empty name.* dwarf2dbg.c (get_filenum): Catch integer wraparound whenextending allocate file array.(dwarf2_directive_filename): Add extra checks of the computed filenumber.* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name intowarning hash table.(s_arm_eabi_attribute): Check for obj_elf_vendor_attributereturning -1.* config/tc-i386.c (i386_output_nops): Catch an attempt togenerate nops of negative lengths.* as.h (MAX_LITTLENUMS): Move definition to here from...* config/atof-ieee.c: ...here.* config/tc-aarch64.c: ...here.* config/tc-arc.c: ...here.* config/tc-arm.c: ...here.* config/tc-epiphany.c: ...here.* config/tc-i386.c: ...here.* config/tc-ia64.c: ...here. (And correct the value).* config/tc-m32c.c: ...here.* config/tc-m32r.c: ...here.* config/tc-metag.c: ...here.* config/tc-microblaze.c: ...here.* config/tc-nds32.c: ...here.* config/tc-or1k.c: ...here.* config/tc-score.c: ...here.* config/tc-score7.c: ...here.* config/tc-tic4x.c: ...here.* config/tc-tilegx.c: ...here.* config/tc-tilepro.c: ...here.* config/tc-visium.c: ...here.* config/tc-sh.c (md_assemble): Add check for an instruction withno opcodes.* config/tc-mips.c (mips_lookup_insn): Add check for very shortinstruction name.* config/tc-tic54x.c: Use unsigned chars to access is_end_of_linearray.(tic54x_start_line_hook): Check for an empty line.(next_line_shows_parallel): Do not walk off the end of the string.(tic54x_macro_start): Check for too much macro nesting.(tic54x_start_label): Add label_start parameter. Use thisparameter to check the first character of the label.* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Passline_start variable to tic54x_start_label.2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:Add expansions for MIPS r6.* testsuite/gas/mips/add.s: Enable tests for R6.* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.* testsuite/gas/mips/mipsr6@add.d: Likewise.* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.* gas/testsuite/gas/mips/mips.exp: Run the new test.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* testsuite/gas/aarch64/sve2.d: Remove file format restriction.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* testsuite/gas/aarch64/illegal-sve2-aes.d: New test.* testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.* testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.* testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.* testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.* testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.* testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.* testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.* testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.* testsuite/gas/aarch64/sve1-extended-sve2.s: New test.* testsuite/gas/aarch64/sve2.d: Test new instructions.* testsuite/gas/aarch64/sve2.s: Test new instructions.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22operand.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEXoperand.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22operand.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.(parse_address_main): Account for new addressing mode [Zn.S, Xm].(parse_operands): Handle new SVE_ADDR_ZX operand.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEXoperand.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>* config/tc-aarch64.c: Add command line architecture feature flags"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".* doc/c-aarch64.texi: Document new architecture feature flags.2019-05-08 Alan Modra <amodra@gmail.com>* testsuite/gas/elf/dwarf2-1.s,* testsuite/gas/elf/dwarf2-2.s,* testsuite/gas/elf/dwarf2-5.s,* testsuite/gas/elf/dwarf2-7.s,* testsuite/gas/elf/dwarf2-8.s,* testsuite/gas/elf/dwarf2-9.s,* testsuite/gas/elf/dwarf2-10.s,* testsuite/gas/elf/dwarf2-11.s,* testsuite/gas/elf/dwarf2-12.s,* testsuite/gas/elf/dwarf2-13.s,* testsuite/gas/elf/dwarf2-14.s,* testsuite/gas/elf/dwarf2-15.s,* testsuite/gas/elf/dwarf2-16.s,* testsuite/gas/elf/dwarf2-17.s,* testsuite/gas/elf/dwarf2-18.s,* testsuite/gas/elf/dwarf2-19.s: Double size of align and simulatedinstructions.* testsuite/gas/elf/dwarf2-1.d,* testsuite/gas/elf/dwarf2-2.d,* testsuite/gas/elf/dwarf2-5.d,* testsuite/gas/elf/dwarf2-7.d,* testsuite/gas/elf/dwarf2-8.d,* testsuite/gas/elf/dwarf2-9.d,* testsuite/gas/elf/dwarf2-10.d,* testsuite/gas/elf/dwarf2-11.d,* testsuite/gas/elf/dwarf2-12.d,* testsuite/gas/elf/dwarf2-13.d,* testsuite/gas/elf/dwarf2-14.d,* testsuite/gas/elf/dwarf2-15.d,* testsuite/gas/elf/dwarf2-16.d,* testsuite/gas/elf/dwarf2-17.d,* testsuite/gas/elf/dwarf2-18.d,* testsuite/gas/elf/dwarf2-19.d: Use xfail rather than notarget.Remove avr, pru, tile, xtensa from xfails. Update expected output.* testsuite/gas/elf/elf.exp: Sort targets.(dump_opts): Pass {as -mno-relax} for riscv, {as -mno-link-relax}for avr and pru, and {as --no-link-relax} for xtensa to dwarf tests.* testsuite/gas/elf/section2.e-miwmmxt: Delete unused file.2019-05-08 Alan Modra <amodra@gmail.com>* config/tc-xtensa.c (opt_linkrelax): New variable.(md_parse_option): Set it here.(md_begin): Copy opt_linkrelax to linkrelax.2019-05-07 Alexandre Oliva <aoliva@redhat.com>* testsuite/gas/elf/dwarf2-18.d: Xfail mep-*.* testsuite/gas/elf/dwarf2-19.d: Likewise.2019-05-07 Alan Modra <amodra@gmail.com>* symbols.c (use_complex_relocs_for): Formatting. Factor outX_add_symbol tests.2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>Faraz Shahbazker <fshahbazker@wavecomp.com>* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.(mips_after_parse_args): Translate EVA to EVA_R6.* testsuite/gas/mips/ase-errors-1.s: Add new instructions.* testsuite/gas/mips/eva.s: Likewise.* testsuite/gas/mips/ase-errors-1.l: Check errors fornew instructions.* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.2019-05-06 Alan Modra <amodra@gmail.com>* symbols.c (symbol_relc_make_sym): Do not access sym->sy_valuedirectly.2019-05-06 Alan Modra <amodra@gmail.com>* config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLTrelocs, and VLE sdarel relocs.* testsuite/gas/ppc/power4.d: Adjust.2019-05-05 Alexandre Oliva <aoliva@redhat.com>* dwarf2dbg.c (set_or_check_view): Skip heads when assigningviews of prior locs.(dwarf2_gen_line_info_1): Skip heads.(size_inc_line_addr, emit_inc_line_addr): DropDW_LNS_advance_pc for zero addr delta.(dwarf2_finish): Assign views for heads of segments.* testsuite/gas/elf/dwarf2-19.d: New.* testsuite/gas/elf/dwarf2-19.s: New.* testsuite/gas/elf/elf.exp: Test it.2019-05-04 Alan Modra <amodra@gmail.com>* config/tc-m32c.c (insn_size): Delete static var.(md_begin): Don't set it.(m32c_md_end): Delete.(md_assemble): Add insn_size auto var.* config/tc-m32c.h (md_end): Don't define.(m32c_md_end): Delete.(NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define.* testsuite/gas/all/align.d: Remove m32c from notarget list.* testsuite/gas/all/incbin.d: Likewise.* testsuite/gas/elf/dwarf2-11.d: Likewise.* testsuite/gas/macros/semi.d: Likewise.* testsuite/gas/all/gas.exp (do_comment): Similarly.2019-05-02 H.J. Lu <hongjiu.lu@intel.com>PR gas/24485* config/tc-i386.c (process_suffix): Issue a warning to IRETwithout a suffix for .code16gcc.* testsuite/gas/i386/jump16.s: Add tests for iretX.* testsuite/gas/i386/jump16.d: Updated.* testsuite/gas/i386/jump16.e: New file.2019-05-01 Sudakshina Das <sudi.das@arm.com>* config/tc-aarch64.c (parse_operands): Add case forAARCH64_OPND_TME_UIMM16.(aarch64_features): Add "tme".* doc/c-aarch64.texi: Document the same.* testsuite/gas/aarch64/tme-invalid.d: New test.* testsuite/gas/aarch64/tme-invalid.l: New test.* testsuite/gas/aarch64/tme-invalid.s: New test.* testsuite/gas/aarch64/tme.d: New test.* testsuite/gas/aarch64/tme.s: New test.2019-04-29 John Darrington <john@darrington.wattle.id.au>* testsuite/gas/s12z/truncated.d: New file.* testsuite/gas/s12z/truncated.s: New file.* testsuite/gas/s12z/s12z.exp: Add new test.2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>Faraz Shahbazker <fshahbazker@wavecomp.com>* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,M_SCDP_AB>: New cases and expansions for paired instructions.* testsuite/gas/mips/llpscp-32.s: New test source.* testsuite/gas/mips/llpscp-64.s: Likewise.* testsuite/gas/mips/llpscp-32.d: New test.* testsuite/gas/mips/llpscp-64.d: Likewise.* testsuite/gas/mips/mips.exp: Run the new tests.* testsuite/gas/mips/r6.s: Add new instructions to test source.* testsuite/gas/mips/r6-64.s: Likewise.* testsuite/gas/mips/r6-64-n32.d: Check new instructions.* testsuite/gas/mips/r6-64-n64.d: Likewise.* testsuite/gas/mips/r6-n32.d: Likewise.* testsuite/gas/mips/r6-n64.d: Likwwise.* testsuite/gas/mips/r6.d: Likewise.2019-04-26 H.J. Lu <hongjiu.lu@intel.com>PR gas/24485* config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODEto IRET for .code16gcc.* testsuite/gas/i386/jump16.s: Add IRET tests.* testsuite/gas/i386/jump16.d: Updated.2019-04-25 Alexandre Oliva <aoliva@redhat.com>Alan Modra <amodra@gmail.com>PR gas/24444* frags.c (frag_gtoffset_p): New.* frags.h (frag_gtoffset_p): Declare it.* expr.c (resolve_expression): Use it.2019-04-24 Alan Modra <amodra@gmail.com>PR 24444* symbols.c (resolve_symbol_value): When handling symbolsmarked as sy_flags.resolved, return correct value for thecase of expression symbols left as an O_symbol expression.Merge O_symbol code handling undefined and common symbols withcode handling special cases of expression symbols. Useseg_left to test for undefined and common symbols. Don'tleave an O_symbol expression when X_add_symbol resolves tothe absolute_section. Init final_val later.* testsuite/gas/mmix/basep-7.d: Adjust expected output.2019-04-24 John Darrington <john@darrington.wattle.id.au>* testsuite/gas/s12z/bit-manip-invalid.s: Extend test for BSETand BCLR instructions with an invalid mode.* testsuite/gas/s12z/bit-manip-invalid.d: ditto.2019-04-19 Nick Clifton <nickc@redhat.com>PR 24464* config/tc-rx.h (md_relax_frag): Pass the max_iterations variableto the relaxation function.* config/tc-rx.c (rx_relax_frag): Add new parameter - the maximumnumber of iterations. Make sure that our internal iteration limitdoes not exceed this external iteration limit.2019-04-18 Matthew Fortune <matthew.fortune@mips.com>* config/tc-mips.c (match_non_zero_reg_operand): Updatewarning message.* testsuite/gas/mips/r6-branch-constraints.l: Likewise.2019-04-18 Jozef Lawrynowicz <jozef.l@mittosystems.com>* config/tc-msp430.c (msp430_make_init_symbols): Define__crt0_run_{preinit,init,fini}_array symbols if.{preinit,init,fini}_array sections exist.* testsuite/gas/msp430/fini-array.d: New test.* testsuite/gas/msp430/init-array.d: New test.* testsuite/gas/msp430/preinit-array.d: New test.* testsuite/gas/msp430/fini-array.s: New test source.* testsuite/gas/msp430/init-array.s: New test source.* testsuite/gas/msp430/preinit-array.s: New test source.* testsuite/gas/msp430/msp430.exp: Add new tests to driver.2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>* config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bsssymbol when .lower.bss or .either.bss sections exist.Define __crt0_movedata when .lower.data or .either.data sections exist.* testsuite/gas/msp430/either-data-bss-sym.d: New test.* testsuite/gas/msp430/low-data-bss-sym.d: New test.* testsuite/gas/msp430/either-data-bss-sym.s: New test source.* testsuite/gas/msp430/low-data-bss-sym.s: New test source.* testsuite/gas/msp430/msp430.exp: Run new tests.Enable large code model when running -mdata-region={upper,either}tests.2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>* config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS,OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops.(md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS andOPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nopsaccordingly.(md_show_usage): Likewise.(md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and"mU" for OPTION_NO_UNKNOWN_INTR_NOPS.(md_longopts): Likewise.(warn_eint_nop): Update comment.(warn_unsure_interrupt): Don't warn if prev_insn_is_nop orprev_insn_is_dint or we are assembling for 430 ISA.(msp430_operands): Only call warn_unsure_interrupt ifdo_unknown_interrupt_nops == TRUE.* testsuite/gas/msp430/nop-unknown-intr.s: New test source file.* testsuite/gas/msp430/nop-unknown-intr-430.d: New test.* testsuite/gas/msp430/nop-unknown-intr-430x.d: New test.* testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test.* testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for newtest.* testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise.* testsuite/gas/msp430/msp430.exp: Add new tests to driver.2019-04-16 Alan Modra <amodra@gmail.com>* testsuite/gas/all/weakref1.d: xfail nds32.2019-04-16 Alan Modra <amodra@gmail.com>* testsuite/gas/all/gas.exp: Remove ns32k xfails.* testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.2019-04-16 Alan Modra <amodra@gmail.com>* write.h: Don't include bit_fix.h.(struct fix): Rearrange some fields. Delete fx_im_disp andfx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust.* write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP.(fixup_segment): Don't exclude overflow checks on fx_bit_fixP.(print_fixup): Don't print im_disp.* config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixPand fx_im_disp.* config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Setfx_no_overflow when fx_bit_fixP.* config/tc-dlx.h: Include bit_fix.h.(TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define.* config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Setfx_no_overflow when bit_fixP.* config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp.(fix_im_disp, fix_bit_fixP): Adjust to suit.(TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.2019-04-16 Alan Modra <amodra@gmail.com>* write.h (struct fix <fx_where>): Make unsigned.(fix_new, fix_at_start, fix_new_exp): Adjust prototypes.* write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and"size" parameters unsigned long.(fix_new_internal): Likewise. Adjust error format string to suit.* config/tc-mips.c (md_convert_frag): Remove cast of fx_where.* config/tc-sparc.c (md_apply_fix): Likewise.* config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where.* config/tc-score7.c (s7_convert_frag): Likewise.2019-04-16 Alan Modra <amodra@gmail.com>* frags.h (struct frag <fr_fix>): Use unsigned type.* frags.c (frag_new): Assert that current size exceedsold_frags_var_max_size.* ehopt.c (get_cie_info): Adjust for unsigned fr_fix.* listing.c (calc_hex): Likewise.* write.c (cvt_frag_to_fill, write_relocs): Likewise.* config/tc-arc.c (md_convert_frag): Likewise.* config/tc-avr.c (avr_patch_gccisr_frag): Likewise.* config/tc-mips.c (md_convert_frag): Likewise.* config/tc-rl78.c (md_convert_frag): Likewise.* config/tc-rx.c (md_convert_frag): Likewise.* config/tc-sparc.c (md_apply_fix): Likewise.* config/tc-xtensa.c (next_instrs_are_b_retw): Likewise.(unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>* config/tc-arm.c (parse_sys_vldr_vstr): New function.(OP_VLDR): New enum operand_parse_code enumerator.(parse_operands): Add logic for OP_VLDR.(do_t_vldr_vstr_sysreg): New function.(do_vldr_vstr): Likewise.(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of baduses of VLDR and VSTR.* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages forabove bad uses.* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR andVSTR valid uses.* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for theabove examples.2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPRenumerators.(parse_vfp_reg_list): Add new partial_match parameter. Set*partial_match to TRUE if at least one element in the register list hasmatched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPRregister lists which expect VPR as last element in the list.(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to newprototype.(s_arm_unwind_save_vfp): Likewise.(enum operand_parse_code): New OP_VRSDVLST enumerator.(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.Handle new OP_VRSDVLST case.(do_t_vscclrm): New function.(insns): New entry for VSCCLRM instruction.* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRMinstructions.* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectationsfor above instructions.* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRMinstruction.* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassemblyfor above instructions.2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>* config/tc-arm.c (enum reg_list_els): Define earlier and addREGLIST_RN and REGLIST_CLRM enumerators.(parse_reg_list): Add etype parameter to distinguish between regularcore register list and CLRM register list. Add logic torecognize CLRM register list.(parse_vfp_reg_list): Assert type is not for core register list.(s_arm_unwind_save_core): Update call to parse_reg_list to newprototype.(enum operand_parse_code): Declare OP_CLRMLST enumerator.(parse_operands): Update call to parse_reg_list to new prototype. Addlogic for OP_CLRMLST.(encode_thumb2_ldmstm): Rename into ...(encode_thumb2_multi): This. Add do_io parameter. Add logic toencode CLRM and guard LDM/STM only code by do_io.(do_t_ldmstm): Adapt to use encode_thumb2_multi.(do_t_push_pop): Likewise.(do_t_clrm): New function.(insns): Define CLRM.* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.2019-04-15 Sudakshina Das <sudi.das@arm.com>Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLRfor the LR operand and optional LR operand.(parse_operands): Add switch cases for OP_LR and OP_oLR forboth type checking and value checking.(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.(v8_1_loop_reloc): New helper function for handling labelsfor the low overhead loop instructions.(do_t_loloop): New function to encode DLS, WLS and LE.(insns): New entries for WLS, DLS and LE.(md_pcrel_from_section): New switch casefor BFD_RELOC_ARM_THUMB_LOOP12.(md_appdy_fix): Likewise.(tc_gen_reloc): Likewise.* testsuite/gas/arm/armv8_1-m-tloop.s: New.* testsuite/gas/arm/armv8_1-m-tloop.d: New.* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.2019-04-15 Sudakshina Das <sudi.das@arm.com>Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.(do_t_v8_1_branch): New switch case for bfcsel.(toU): Define.(insns): New instruction for bfcsel.(md_pcrel_from_section): New switch casefor BFD_RELOC_THUMB_PCREL_BFCSEL.(md_appdy_fix): Likewise(tc_gen_reloc): Likewise.* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.2019-04-15 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (md_pcrel_from_section): New switch case forBFD_RELOC_ARM_THUMB_BF13.(md_appdy_fix): Likewise.(tc_gen_reloc): Likewise.2019-04-15 Sudakshina Das <sudi.das@arm.com>Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (T16_32_TAB): New entrie for bfl.(do_t_v8_1_branch): New switch case for bfl.(insns): New instruction for bfl.* testsuite/gas/arm/armv8_1-m-bfl.d: New.* testsuite/gas/arm/armv8_1-m-bfl.s: New.* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.2019-04-15 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (md_pcrel_from_section): New switch case forBFD_RELOC_ARM_THUMB_BF19.(md_appdy_fix): Likewise.(tc_gen_reloc): Likewise.2019-04-15 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.(do_t_v8_1_branch): New switch cases for bfx and bflx.(insns): New instruction for bfx and bflx.* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New2019-04-15 Sudakshina Das <sudi.das@arm.com>Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (T16_32_TAB): New entries for bf.(do_t_branch_future): New.(insns): New instruction for bf.* testsuite/gas/arm/armv8_1-m-bf.d: New.* testsuite/gas/arm/armv8_1-m-bf.s: New.* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.2019-04-15 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (md_pcrel_from_section): New switch case forBFD_RELOC_ARM_THUMB_BF17.(md_appdy_fix): Likewise.(tc_gen_reloc): Likewise.2019-04-15 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro.(arm_it): Member reloc renamed relocs and updated to an array.Rest: Replace all occurrences of reloc to relocs[0].2019-04-15 Sudakshina Das <sudi.das@arm.com>* config/tc-arm.c (md_pcrel_from_section): New switch casefor BFD_RELOC_THUMB_PCREL_BRANCH5.(v8_1_branch_value_check): New function to check branchoffsets.(md_appdy_fix): New switch case forBFD_RELOC_THUMB_PCREL_BRANCH5.(tc_gen_reloc): Likewise.2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.(armv8_1m_main_ext_table): New extension table.(arm_archs): Use the new extension table.* doc/c-arm.texi: Add missing arch and document new extensions.* testsuite/gas/arm/armv8.1-m.main-fp.d: New.* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.* testsuite/gas/arm/armv8.1-m.main-hp.d: New.2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M MainlineTag_CPU_arch build attribute value. Reindent.(get_aeabi_cpu_arch_from_fset): Update assert.(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.2019-04-09 Matthew Fortune <matthew.fortune@mips.com>* config/tc-mips.c (mips_cpu_info_table): Add i6500. Updatedefault ASEs for i6400.* doc/c-mips.texi (-march): Document i6500.* testsuite/gas/mips/elf_mach_i6400.d: New test.* testsuite/gas/mips/elf_mach_i6500.d: New test.* testsuite/gas/mips/mips.exp: Run the new tests.2019-04-09 Matthew Fortune <matthew.fortune@mips.com>* config/tc-mips.c (mips_set_options) <init_ase>: New field.(file_mips_opts, mips_opts) <init_ase>: Initialize new field.(file_mips_check_options): Propagate initial ASE settings.(mips_after_parse_args, parse_code_option): Track the initialASE settings for a CPU.(s_mipsset): Restore the initial ASE settings when revertingto the default arch.* testsuite/gas/mips/elf_mach_p6600.d: New test.* testsuite/gas/mips/mips.exp: Run the new test.2019-04-12 John Darrington <john@darrington.wattle.id.au>config/tc-s12z.h: Remove definition of macro TC_M68K2019-04-01 John Darrington <john@darrington.wattle.id.au>config/tc-s12z.c: Use bfd_boolean where appropriate.2019-04-11 Max Filippov <jcmvbkbc@gmail.com>* testsuite/gas/xtensa/loop-relax-2.d: New test definition.* testsuite/gas/xtensa/loop-relax.d: New test definition.* testsuite/gas/xtensa/loop-relax.s: New test source.* testsuite/gas/xtensa/text-section-literals-1a.d: New testdefinition.* testsuite/gas/xtensa/text-section-literals-2.d: New testdefinition.* testsuite/gas/xtensa/text-section-literals-2.s: New testsource.* testsuite/gas/xtensa/text-section-literals-2a.d: New testdefinition.* testsuite/gas/xtensa/text-section-literals-3.d: New testdefinition.* testsuite/gas/xtensa/text-section-literals-3.s: New testsource.* testsuite/gas/xtensa/text-section-literals-4.d: New testdefinition.* testsuite/gas/xtensa/text-section-literals-4.s: New testsource.* testsuite/gas/xtensa/text-section-literals-4a.d: New testdefinition.2019-04-11 Max Filippov <jcmvbkbc@gmail.com>* testsuite/gas/xtensa/all.exp: Remove all expect-basedtests and all explicit run_dump_test / run_list_testinvocations. Add run_dump_tests for all .d files in thetest subdirectory.* testsuite/gas/xtensa/entry_align.d: New test definition.* testsuite/gas/xtensa/entry_align.l: New test output.* testsuite/gas/xtensa/entry_misalign.d: New test definition.* testsuite/gas/xtensa/entry_misalign2.d: New test definition.* testsuite/gas/xtensa/j_too_far.d: New test definition.* testsuite/gas/xtensa/j_too_far.l: New test output.* testsuite/gas/xtensa/loop_align.d: New test definition.* testsuite/gas/xtensa/loop_misalign.d: New test definition.* testsuite/gas/xtensa/trampoline-2.d: New test definition.* testsuite/gas/xtensa/trampoline-2.l: Remove empty output.* testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.2019-04-11 Max Filippov <jcmvbkbc@gmail.com>* config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that hasno effect.(get_literal_pool_location): Only search for the literal poolwhen auto litpools is used, otherwise take one recorded in thetc_segment_info_data.(xtensa_assign_litpool_addresses): New function.(xtensa_move_literals): Don't duplicate 'literal pool locationrequired...' error message. Call xtensa_assign_litpool_addresses.2019-04-11 Max Filippov <jcmvbkbc@gmail.com>* config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.(xtensa_mark_literal_pool_location): Don't add fill frag to literalsection that records literal pool location.(md_begin): Call xtensa_mark_literal_pool_location when textsection literals or auto litpools are used.(xtensa_elf_section_change_hook): Callxtensa_mark_literal_pool_location when text section literals orauto litpools are used, there's no literal pool location definedfor the current section and it's not .init or .fini.* testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.* testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.* testsuite/gas/xtensa/auto-litpools.d: Likewise.2019-04-11 Sudakshina Das <sudi.das@arm.com>* config/tc-aarch64.c (process_omitted_operand): Add case forAARCH64_OPND_Rt_SP.(parse_operands): Likewise.* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.* testsuite/gas/aarch64/illegal-memtag.l: Likewise.* testsuite/gas/aarch64/illegal-memtag.s: Likewise.2019-04-11 Sudakshina Das <sudi.das@arm.com>* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.* testsuite/gas/aarch64/illegal-memtag.l: Likewise.* testsuite/gas/aarch64/illegal-memtag.s: Likewise.2019-04-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>* config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.* testsuite/gas/i386/solaris/solaris.exp: New driver.* testsuite/gas/i386/solaris/reloc64.d,testsuite/gas/i386/solaris/x86-64-jump.d,testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,testsuite/gas/i386/solaris/x86-64-nop-3.d,testsuite/gas/i386/solaris/x86-64-nop-4.d,testsuite/gas/i386/solaris/x86-64-nop-5.d,testsuite/gas/i386/solaris/x86-64-relax-2.d,testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.* testsuite/gas/i386/reloc64.d,testsuite/gas/i386/x86-64-jump.d,testsuite/gas/i386/x86-64-mpx-branch-1.d,testsuite/gas/i386/x86-64-mpx-branch-2.d,testsuite/gas/i386/x86-64-nop-3.d,testsuite/gas/i386/x86-64-nop-4.d,testsuite/gas/i386/x86-64-nop-5.d,testsuite/gas/i386/x86-64-relax-2.d,testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.2019-04-10 Alan Modra <amodra@gmail.com>* config/te-cloudabi.h: New file.* config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABIrather than TARGET_OS to select cloudabi.* config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI.* configure.tgt (*-*-cloudabi*): Set em=cloudabi.2019-04-09 Robert Suchanek <robert.suchanek@mips.com>* testsuite/gas/mips/mips.exp: Run hwr-names test.* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR withthe SEL field.* testsuite/gas/mips/mipsr6@hwr-names.d: New file.2019-04-08 H.J. Lu <hongjiu.lu@intel.com>* config/tc-i386.c (output_insn): SupportGNU_PROPERTY_X86_ISA_1_AVX512_BF16.* testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.* testsuite/gas/i386/property-2.d: Updated.* testsuite/gas/i386/x86-64-property-2.d: Likewise.2019-04-08 H.J. Lu <hongjiu.lu@intel.com>* configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets.* testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos*check.2019-04-05 H.J. Lu <hongjiu.lu@intel.com>* testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests.* testsuite/gas/i386/property-2.d: New file.* testsuite/gas/i386/property-2.s: Likewise.* testsuite/gas/i386/x86-64-property-2.d: Likewise.2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>* config/tc-i386.c (cpu_arch): Add .avx512_bf16.(cpu_noarch): Add noavx512_bf16.* doc/c-i386.texi: Document avx512_bf16.* testsuite/gas/i386/avx512_bf16.d: New file.* testsuite/gas/i386/avx512_bf16.s: Likewise.* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.* testsuite/gas/i386/i386.exp: Add BF16 related tests.2019-04-05 Alan Modra <amodra@gmail.com>* testsuite/gas/ppc/bc.s,* testsuite/gas/ppc/bcat.d,* testsuite/gas/ppc/bcaterr.d,* testsuite/gas/ppc/bcaterr.l,* testsuite/gas/ppc/bcy.d,* testsuite/gas/ppc/bcyerr.d,* testsuite/gas/ppc/bcyerr.l: New tests.* testsuite/gas/ppc/ppc.exp: Run them.2019-04-05 Alan Modra <amodra@gmail.com>* testsuite/gas/ppc/476.d: Remove trailing spaces.* testsuite/gas/ppc/a2.d: Likewise.* testsuite/gas/ppc/booke.d: Likewise.* testsuite/gas/ppc/booke_xcoff.d: Likewise.* testsuite/gas/ppc/e500.d: Likewise.* testsuite/gas/ppc/e500mc.d: Likewise.* testsuite/gas/ppc/e6500.d: Likewise.* testsuite/gas/ppc/htm.d: Likewise.* testsuite/gas/ppc/power6.d: Likewise.* testsuite/gas/ppc/power8.d: Likewise.* testsuite/gas/ppc/power9.d: Likewise.* testsuite/gas/ppc/vle.d: Likewise.2019-04-04 Peter Bergner <bergner@linux.ibm.com>PR gas/24349* testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,bttarl+): Add tests of extended mnemonics.* testsuite/gas/ppc/power8.d: Likewise. Update previous bctar teststo expect new extended mnemonics.* testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update testto not use illegal BO value. Use a more convenient BI value.* testsuite/gas/ppc/a2.d: Update tests for new expect output.2019-04-03 Max Filippov <jcmvbkbc@gmail.com>* config/tc-xtensa.c (convert_frag_immed): Dropconvert_frag_immed_finish_loop invocation.(convert_frag_immed_finish_loop): Drop declaration anddefinition.* config/xtensa-relax.c (widen_spec_list): Replace loopwidening that uses addi/addmi with widening that uses l32rand const16.2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>* config/tc-arm.c (arm_ext_table): New struct type.(arm_arch_option_table): Add new 'arm_ext_table' field.(ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.(armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,armv85a_ext_table, armv8m_main_ext_table,armv8r_ext_table): New architecture extension tables.(ARM_ARCH_OPT): Add new default field.(ARM_ARCH_OPT2): New macro.(arm_archs): Extend some architectures with the new architectureextension tables mentioned above.(arm_extensions): Add DEPRECATED comment with instructions touse new table.(arm_parse_extension): Change to use new extension tables.(arm_parse_cpu): Don't change existing behavior.(arm_parse_arch): Change to use new extension tables.* doc/c-arm.texi: Document new architecture extensions.* testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use newextension option rather than -mfpu and change expected behaviour tosane outputs.* testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.* testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.* testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.* testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.* testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.* testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.* testsuite/gas/arm/armv8_2+rdma-ext.d: New.* testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.* testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.* testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.* testsuite/gas/arm/armv8_3-a-fp-ext.d: New.* testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.* testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.* testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.* testsuite/gas/arm/armv8m.main+fp.d: New.* testsuite/gas/arm/armv8m.main+fp.dp.d: New.* testsuite/gas/arm/attr-ext-fpv5-d16.d: New.* testsuite/gas/arm/attr-ext-fpv5.d: New.* testsuite/gas/arm/attr-ext-idiv.d: New.* testsuite/gas/arm/attr-ext-mp.d: New.* testsuite/gas/arm/attr-ext-neon-fp16.d: New.* testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.* testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.* testsuite/gas/arm/attr-ext-sec.d: New.* testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.* testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.* testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.* testsuite/gas/arm/attr-ext-vfpv3.d: New.* testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.* testsuite/gas/arm/attr-ext-vfpv3xd.d: New.* testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.* testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.* testsuite/gas/arm/attr-ext-vfpv4.d: New.* testsuite/gas/arm/dotprod-mandatory-ext.d: New.* testsuite/gas/arm/fpv5-d16.s: New.* testsuite/gas/arm/fpv5-sp-d16.s: New.2019-03-28 Alan Modra <amodra@gmail.com>PR 24390* testsuite/gas/ppc/476.d: Update mtfsb*.* testsuite/gas/ppc/a2.d: Likewise.2019-03-21 Alan Modra <amodra@gmail.com>* emul.h (struct emulation): Delete strip_underscore.* emul-target.h (emul_strip_underscore): Don't define.(emul_struct_name): Update initialization.2019-03-21 Alan Modra <amodra@gmail.com>* config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.* config/tc-pdp11.c (md_apply_fix): Likewise.* config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,BFD_RELOC_16, and BFD_RELOC_64.* testsuite/gas/all/gas.exp: Move target exclusions for forwardtest, but not cr16, to..* testsuite/gas/all/forward.d: ..here, with explanation. Removed10v, d30v, and pdp11 xfails.2019-03-19 H.J. Lu <hongjiu.lu@intel.com>* config/tc-i386.c (optimize_encoding): Don't check AVX forEVEX vector load/store optimization. Check both operands forZMM register. Update EVEX vector load/store opcode check.Choose EVEX Disp8 over VEX Disp32.* testsuite/gas/i386/optimize-1.d: Updated.* testsuite/gas/i386/optimize-1a.d: Likewise.* testsuite/gas/i386/optimize-2.d: Likewise.* testsuite/gas/i386/optimize-4.d: Likewise.* testsuite/gas/i386/optimize-5.d: Likewise.* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.* testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.* testsuite/gas/i386/optimize-1.s: Add ZMM register loadtest.* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.2019-03-19 H.J. Lu <hongjiu.lu@intel.com>PR gas/24352* config/tc-i386.c (optimize_encoding): Check onlycpu_arch_flags.bitfield.cpuavx512vl.* testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.* testsuite/gas/i386/x86-64-optimize-2.d: Revert the lastchange.* testsuite/gas/i386/x86-64-optimize-2b.d: New file.* testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.2019-03-19 H.J. Lu <hongjiu.lu@intel.com>PR gas/24359* testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.Remove optimize-6c and x86-64-optimize-7c tests.* testsuite/gas/i386/noavx-3.l: Updated.* testsuite/gas/i386/noavx-4.d: Likewise.* testsuite/gas/i386/noavx-5.d: Likewise.* testsuite/gas/i386/noavx-3.s: Add AVX512F tests.* testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.* testsuite/gas/i386/nosse-5.s: Likewise.* testsuite/gas/i386/optimize-6a.d: Removed.* testsuite/gas/i386/optimize-6c.d: Likewise.* testsuite/gas/i386/optimize-7.d: Likewise.* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.* testsuite/gas/i386/optimize-6a.l: New file.* testsuite/gas/i386/optimize-6a.s: Likewise.* testsuite/gas/i386/optimize-7.l: Likewise.* testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.* testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.* testsuite/gas/i386/x86-64-optimize-8.l: Likewise.2019-03-18 Alan Modra <amodra@gmail.com>* config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.* as.c (macro_expr): Likewise.* macro.c (buffer_and_nest): Likewise.* read.c (temp_ilp): Remove FIXME.2019-03-18 H.J. Lu <hongjiu.lu@intel.com>* testsuite/gas/i386/att-regs.d: Pass -O0 to assembler.* testsuite/gas/i386/avx512bw-intel.d: Likewise.* testsuite/gas/i386/avx512bw.d: Likewise.* testsuite/gas/i386/avx512f-intel.d: Likewise.* testsuite/gas/i386/avx512f.d: Likewise.* testsuite/gas/i386/disp32.d: Likewise.* testsuite/gas/i386/intel-regs.d: Likewise.* testsuite/gas/i386/pseudos.d: Likewise.* testsuite/gas/i386/x86-64-disp32.d: Likewise.* testsuite/gas/i386/x86-64-pseudos.d: Likewise.2019-03-18 H.J. Lu <hongjiu.lu@intel.com>PR gas/24348* config/tc-i386.c (optimize_encoding): Encode 128-bit and256-bit EVEX vector register load/store instructions as VEXvector register load/store instructions for -O1.* doc/c-i386.texi: Update -O1 documentation.* testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.* testsuite/gas/i386/optimize-1.s: Add tests for EVEX vectorload/store instructions.* testsuite/gas/i386/optimize-2.s: Likewise.* testsuite/gas/i386/optimize-3.s: Likewise.* testsuite/gas/i386/optimize-5.s: Likewise.* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.* testsuite/gas/i386/optimize-1.d: Updated.* testsuite/gas/i386/optimize-2.d: Likewise.* testsuite/gas/i386/optimize-3.d: Likewise.* testsuite/gas/i386/optimize-4.d: Likewise.* testsuite/gas/i386/optimize-5.d: Likewise.* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.* testsuite/gas/i386/optimize-7.d: New file.* testsuite/gas/i386/optimize-7.s: Likewise.* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.* testsuite/gas/i386/x86-64-optimize-8.s: Likewise.2019-03-18 H.J. Lu <hongjiu.lu@intel.com>* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bitVEX/EVEX vector register clearing instructions with 128-bit VEXvector register clearing instructions at -O1.* doc/c-i386.texi: Update -O1 and -O2 documentation.* testsuite/gas/i386/i386.exp: Run optimize-1a andx86-64-optimize-2a.* testsuite/gas/i386/optimize-1a.d: New file.* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.2019-03-17 H.J. Lu <hongjiu.lu@intel.com>PR gas/24353* config/tc-i386.c: Include <limits.h> if it exists and tryincluding <sys/param.h> if we have it.(INT_MAX): Define if not defined.(md_parse_option): Set optimize to INT_MAX for -Os.* testsuite/gas/i386/optimize-2.s: Add a test.* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.* testsuite/gas/i386/optimize-2.d: Updated.* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.2019-03-17 H.J. Lu <hongjiu.lu@intel.com>PR gas/24352* config/tc-i386.c (optimize_encoding): Encode 512-bit EVEXwith 128-bit VEX encoding only when AVX is enabled and with128-bit EVEX encoding only when AVX512VL is enabled.* testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.* testsuite/gas/i386/optimize-6.s: New file.* testsuite/gas/i386/optimize-6a.d: Likewise.* testsuite/gas/i386/optimize-6b.d: Likewise.* testsuite/gas/i386/optimize-6c.d: Likewise.* testsuite/gas/i386/x86-64-optimize-7.s: Likewise.* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.* testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.* testsuite/gas/i386/x86-64-optimize-2.d: Updated.2019-03-15 Li Hao <li.hao296@zte.com.cn>PR 24308* config/tc-i386.c (parse_insn): Check mnemp before using it todetermine if a suffix can be trimmed.2019-03-13 Christian Eggers <ceggers@gmx.de>* dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.2019-03-13 Christian Eggers <ceggers@gmx.de>* dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.2019-03-13 Christian Eggers <ceggers@gmx.de>* dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.2019-03-13 Christian Eggers <ceggers@gmx.de>* dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.2019-03-13 Christian Eggers <ceggers@gmx.de>* dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers.(out_debug_aranges, out_debug_info): Likewise.2019-03-13 Christian Eggers <ceggers@gmx.de>* symbols.h (symbol_temp_new_now_octets): Declare.(symbol_set_value_now_octets, symbol_octets_p): Declare.* symbols.c (struct symbol_flags): New member sy_octets.(symbol_temp_new_now_octets): New function.(resolve_symbol_value): Return octets instead of bytes ifsy_octets is set.(symbol_set_value_now_octets): New function.(symbol_octets_p): New function.2019-03-13 Christian Eggers <ceggers@gmx.de>* dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>* testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes.* testsuite/gas/s390/zarch-arch13.d: Likewise.2019-02-27 Matthew Malcomson <matthew.malcomson@arm.com>* testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines.* testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove.* testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove.* testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as"lines.* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove.* testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.2019-02-24 Alan Modra <amodra@gmail.com>* config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.2019-02-24 Alan Modra <amodra@gmail.com>PR 24144* config/obj-aout.c (obj_aout_frob_file_before_fix): Write to endof section to ensure file contents cover aligned section size.2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* config/tc-arm.c (arm_cpus): Add neoverse-n1.* doc/c-arm.texi (-mcpu): Document neoverse-n1 value.2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1.* doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1.* doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.2019-02-19 Paul Hua <paul.hua.gm@gmail.com>* NEWS: Mention -m[no-]fix-loongson3-llsc.* configure.ac: Add --enable-mips-fix-loongson3-llsc.Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC.* config.in: Regenerated.* configure: Likewise.* config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc):New variables.(options): New OPTION_FIX_LOONGSON3_LLSC,OPTION_NO_FIX_LOONGSON3_LLSC.(md_longopts): Add -m[no-]fix-loongson3-llsc.(md_begin): Initialize sync insn.(fix_loongson3_llsc): New.(append_insn): Call fix_loongson3_llsc.(md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC,OPTION_NO_FIX_LOONGSON3_LLSC.(md_show_usage): Display -m[no-]fix-loongson3-llsc.* doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc,--enable-mips-fix-loongson3-llsc=[yes|no].2019-02-10 H.J. Lu <hongjiu.lu@intel.com>PR gas/24165* frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT asmax_bytes.* config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes toaarch64_init_frag.* /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes toarm_init_frag.* config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes.* config/tc-ia64.h (TC_FRAG_INIT): Likewise.* config/tc-mmix.h (TC_FRAG_INIT): Likewise.* config/tc-nds32.h (TC_FRAG_INIT): Likewise.* config/tc-ns32k.h (TC_FRAG_INIT): Likewise.* config/tc-rl78.h (TC_FRAG_INIT): Likewise.* config/tc-rx.h (TC_FRAG_INIT): Likewise.* config/tc-score.h (TC_FRAG_INIT): Likewise.* config/tc-tic54x.h (TC_FRAG_INIT): Likewise.* config/tc-tic6x.h (TC_FRAG_INIT): Likewise.* config/tc-xtensa.h (TC_FRAG_INIT): Likewise.* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to(alignment ? ((1 << alignment) - 1) : 1)(i386_tc_frag_data): Add max_bytes.(TC_FRAG_INIT): Add and track max_bytes.(HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE withfragP->tc_frag_data.max_bytes.* doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.2019-02-08 Jim Wilson <jimw@sifive.com>* config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.(riscv_ip) <'C'>: Add 'z' support.2019-02-07 Tamar Christina <tamar.christina@arm.com>* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT forhlt to armv1.* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs* testsuite/gas/arm/hlt.d: New test.* testsuite/gas/arm/hlt.s: New test.2019-02-07 Tamar Christina <tamar.christina@arm.com>* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.* testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.2019-02-07 Tamar Christina <tamar.christina@arm.com>PR binutils/23212* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.2019-02-07 Eric Botcazou <ebotcazou@adacore.com>* config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on64-bit boundaries for the GR6.* testsuite/gas/visium/allinsn_gr6.s: Tweak.* testsuite/gas/visium/allinsn_gr6.d: Likewise.* testsuite/gas/visium/bra-1.d: New test.* testsuite/gas/visium/bra-1.s: Likewise.* testsuite/gas/visium/visium.exp: Run bra-1 test.2019-01-31 John Darrington <john@darrington.wattle.id.au>* config/tc-s12z.c (lex_imm): Add new argument exp_o.(emit_reloc): New function.(md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that itcan be either 2 bytes or 3 bytes long.* testsuite/gas/s12z/mov-imm-reloc.d: New file.* testsuite/gas/s12z/mov-imm-reloc.s: New file.* testsuite/gas/s12z/s12z.exp: Add them.2019-01-31 John Darrington <john@darrington.wattle.id.au>* config/tc-s12z.c (md_apply_fix): Fix incorrect limits.* testsuite/gas/s12z/pc-rel-bad.d: New file.* testsuite/gas/s12z/pc-rel-bad.l: New file.* testsuite/gas/s12z/pc-rel-bad.s: New file.* testsuite/gas/s12z/pc-rel-good.d: New file.* testsuite/gas/s12z/pc-rel-good.s: New file.* testsuite/gas/s12z/s12z.exp: Add them.2019-01-31 John Darrington <john@darrington.wattle.id.au>* config/tc-s12z.c (tfr): Emit warning if operands are the same.* testsuite/gas/s12z/exg.d: New test case.* testsuite/gas/s12z/exg.l: New file.2019-01-31 John Darrington <john@darrington.wattle.id.au>* config/tc-s12z.c (lex_opr): Add a parameter to indicate whetherimmediate mode operands should be permitted.* testsuite/s12z/imm-dest.d: New file.* testsuite/s12z/imm-dest.l: New file.* testsuite/s12z/imm-dest.s: New file.* testsuite/s12z/s12z.exp: Add them.2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>* config/tc-s390.c (s390_parse_cpu): New entry for arch13.* doc/c-s390.texi: Document arch13 march option.* testsuite/gas/s390/s390.exp: Run the arch13 related tests.* testsuite/gas/s390/zarch-arch13.d: New test.* testsuite/gas/s390/zarch-arch13.s: New test.* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonicsalso for z13.2019-01-31 Alan Modra <amodra@gmail.com>* config/tc-alpha.c (md_apply_fix): Correct range checks forBFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR.* config/tc-arm.c (md_apply_fix): Use llabs rather than abs.* config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.2019-01-28 Max Filippov <jcmvbkbc@gmail.com>* config/tc-xtensa.c (md_apply_fix): Mark fixups for constantsymbols as done in md_apply_fix.* testsuite/gas/all/forward.d: Don't XFAIL for xtensa.2019-01-28 Nick Clifton <nickc@redhat.com>* po/fr.po: Updated French translation.* po/ru.po: Updated Russian translation.2019-01-28 Alan Modra <amodra@gmail.com>* configure.ac (ac_checking): Set from bfd/development.shdevelopment variable.* configure: Regenerate.2019-01-25 Sudakshina Das <sudi.das@arm.com>* config/tc-aarch64.c (warn_unpredictable_ldst): Exemptstg, st2g, stzg and stz2g from Xt == Xn with writeback warning.* testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests forstg, stzg, st2g and stz2g.* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.* testsuite/gas/aarch64/illegal-memtag.l: Likewise.* testsuite/gas/aarch64/illegal-memtag.s: Likewise.2019-01-25 Sudakshina Das <sudi.das@arm.com>* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.* testsuite/gas/aarch64/illegal-memtag.l: Likewise.* testsuite/gas/aarch64/illegal-memtag.s: Likewise.2019-01-25 Sudakshina Das <sudi.das@arm.com>Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>* config/tc-aarch64.c (parse_address_main): Remove support for[base]! address expression.(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.(warn_unpredictable_ldst): Remove support for ldstgv_indexed.* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgvand stgv.* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.* testsuite/gas/aarch64/illegal-memtag.l: Likewise.* testsuite/gas/aarch64/illegal-memtag.s: Likewise.2019-01-25 Wu Heng <wu.heng@zte.com.cn>PR gas/23940* macro.c (getstring): Check array bound before accessing.2019-01-25 Alan Modra <amodra@gmail.com>PR 20902PR 24125* read.c (stringer): Delete assertion.2019-01-21 Nick Clifton <nickc@redhat.com>* po/uk.po: Updated Ukranian translation.2019-01-19 Nick Clifton <nickc@redhat.com>* config.in: Regenerate.* configure: Regenerate.* po/gas.pot: Regenerate.2018-06-24 Nick Clifton <nickc@redhat.com>2.32 branch created.2019-01-17 Tamar Christina <tamar.christina@arm.com>* testsuite/gas/arm/archv6t2-1-pe.d: New test.* testsuite/gas/arm/archv6t2-1.d: Skip pe.* testsuite/gas/arm/csdb.d: Skip pe.* testsuite/gas/arm/sb-thumb1-pe.d: New test.* testsuite/gas/arm/sb-thumb1.d: Skip pe.* testsuite/gas/arm/sb-thumb2-pe.d: New test.* testsuite/gas/arm/sb-thumb2.d: Skip pe.* testsuite/gas/arm/udf.d: Skip pe.2019-01-16 Kito Cheng <kito@andestech.com>* testsuite/gas/riscv/attribute-empty.d: New.2019-01-16 Kito Cheng <kito@andestech.com>Nelson Chu <nelson@andestech.com>* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.(riscv_set_options): Add `arch_attr` field.(riscv_opts): Set default value for arch_attr.(riscv_write_out_arch_attr): New.(riscv_set_public_attributes): Likewise.(riscv_md_end): Likewise.(riscv_convert_symbolic_attribute): Likewise.(s_riscv_attribute): Likewise.(explicit_arch_attr): Likewise.(riscv_pseudo_table): Add .attribute to the table.(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTRenumeration constants.(md_longopts): Add `march-attr' and `mno-arch-attr' options.(md_parse_option): Handle the new options.(md_show_usage): Document the `march-attr' option.* config/tc-riscv.h (md_end): Define as riscv_md_end(riscv_md_end): Declare.(CONVERT_SYMBOLIC_ATTRIBUTE): Define asriscv_convert_symbolic_attribute.(riscv_convert_symbolic_attribute): Declare.(start_assemble): Declare.* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.* testsuite/gas/elf/section2.e-riscv: New.* testsuite/gas/riscv/attribute-01.d: New test* testsuite/gas/riscv/attribute-02.d: Likewise.* testsuite/gas/riscv/attribute-03.d: Likewise.* testsuite/gas/riscv/attribute-04.d: Likewise.* testsuite/gas/riscv/attribute-04.s: Likewise.* testsuite/gas/riscv/attribute-05.d: Likewise.* testsuite/gas/riscv/attribute-05.s: Likewise.* testsuite/gas/riscv/attribute-06.d: Likewise.* testsuite/gas/riscv/attribute-06.s: Likewise.* testsuite/gas/riscv/attribute-07.d: Likewise.* testsuite/gas/riscv/attribute-07.s: Likewise.* testsuite/gas/riscv/attribute-08.d: Likewise.* testsuite/gas/riscv/attribute-08.s: Likewise.* testsuite/gas/riscv/attribute-unknown.d: Likewise.* testsuite/gas/riscv/attribute-unknown.s: Likewise.* testsuite/gas/riscv/empty.l: Likewise.* doc/c-riscv.texi (.attribute): Add documentation.* configure.ac (--enable-default-riscv-attribute): New options.* configure: Re-generate.* config.in: Re-generate.2019-01-16 John Darrington <john@darrington.wattle.id.au>* config/tc-s12z.c (lex_reg_name): Compare the length of the stringsbefore the contents.* testsuite/gas/s12z/labels.d: New file.* testsuite/gas/s12z/labels.s: New file.* testsuite/gas/s12z/s12z.exp: Add them.* config/tc-s12z.c (tfr): Change as_bad to as_warn.Also fix message typo and semantics.* config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead ofBFD_RELOC_24.* testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR insteadof R_S12Z_EXT24.2019-01-14 Srinath Parvathaneni <srinath.parvathaneni@arm.com>* config/tc-arm.c (arm_ext_v6k_v6t2): Define.(insns) [ARM_VARIANT]: Modified.(insns) [THUMB_VARIANT]: To implement few ARMv6K instructionsin ARMv6T2 as well.* testsuite/gas/arm/archv6t2-1.d: New test.* testsuite/gas/arm/archv6t2-1.s: Likewise.* testsuite/gas/arm/archv6t2-2.d: Likewise.2019-01-11 Alan Modra <amodra@gmail.com>PR 23963* testsuite/gas/m68hc11/lbranch-dwarf2.d: Adjust for PR23963 change.* testsuite/gas/m68hc11/opers12-dwarf2.d: Likewise.2019-01-10 Nick Clifton <nickc@redhat.com>PR 23963* testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for thefact that control characters are now displayed as escapesequences.* testsuite/gas/mips/mips16-e.d: Likewise.* testsuite/gas/mips/mips16-pcrel-0.d: Likewise.* testsuite/gas/mips/mips16-pcrel-1.d: Likewise.* testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise.* testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise.* testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise.* testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise.* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise.* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d:Likewise.* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d:Likewise.* testsuite/gas/mips/mipsel16-e.d: Likewise.* testsuite/gas/mips/mipsr6@msa.d: Likewise.* testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise.* testsuite/gas/mips/r6-64-n32.d: Likewise.* testsuite/gas/mips/r6-64-n64.d: Likewise.* testsuite/gas/mips/r6-n32.d: Likewise.* testsuite/gas/mips/r6-n64.d: Likewise.* testsuite/gas/mips/r6.d: Likewise.* testsuite/gas/mips/tmips16-e.d: Likewise.* testsuite/gas/mips/tmipsel16-e.d: Likewise.* testsuite/gas/mn10300/relax.d: Likewise.2019-01-09 John Darrington <john@darrington.wattle.id.au>* testsuite/gas/s12z/jsr.s: New case.* testsuite/gas/s12z/jsr.d: New case.2019-01-09 Andrew Paprocki <andrew@ishiboo.com>* configure: Regenerate.2019-01-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* config/tc-aarch64.c (aarch64_cpus): Add ares.* doc/c-aarch64.texi (-mcpu): Document ares value.2019-01-08 Alan Modra <amodra@gmail.com>* testsuite/gas/rx/rx.exp: Create generated test source incurrent directory.* testsuite/gas/rx/Xtod.d, * testsuite/gas/rx/abs.d,* testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d,* testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d,* testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bfmov.d,* testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d,* testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d,* testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d,* testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d,* testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dabs.d,* testsuite/gas/rx/dadd.d, * testsuite/gas/rx/dbt.d,* testsuite/gas/rx/dcmp.d, * testsuite/gas/rx/ddiv.d,* testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d,* testsuite/gas/rx/dmov.d, * testsuite/gas/rx/dmul.d,* testsuite/gas/rx/dneg.d, * testsuite/gas/rx/dpopm.d,* testsuite/gas/rx/dpushm.d, * testsuite/gas/rx/dround.d,* testsuite/gas/rx/dsqrt.d, * testsuite/gas/rx/dsub.d,* testsuite/gas/rx/dtoX.d, * testsuite/gas/rx/emaca.d,* testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d,* testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d,* testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d,* testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d,* testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d,* testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d,* testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d,* testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d,* testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d,* testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d,* testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d,* testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d,* testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d,* testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d,* testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d,* testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d,* testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d,* testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d,* testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d,* testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvfdc.d,* testsuite/gas/rx/mvfdr.d, * testsuite/gas/rx/mvtacgu.d,* testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d,* testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d,* testsuite/gas/rx/mvtdc.d, * testsuite/gas/rx/neg.d,* testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d,* testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d,* testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d,* testsuite/gas/rx/popm.d, * testsuite/gas/rx/push.d,* testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d,* testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d,* testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d,* testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d,* testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d,* testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d,* testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d,* testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d,* testsuite/gas/rx/rstr.d, * testsuite/gas/rx/rte.d,* testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d,* testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d,* testsuite/gas/rx/satr.d, * testsuite/gas/rx/save.d,* testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d,* testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d,* testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d,* testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d,* testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d,* testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d,* testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d,* testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d,* testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d,* testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d,* testsuite/gas/rx/xor.d: Add #source line.2019-01-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>* config/tc-arm.c (arm_cpus): Add ares.* doc/c-arm.texi (-mcpu): Document ares value.2019-01-05 Yoshinori Sato <ysato@users.sourceforge.jp>* config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.(rx_bfield): Add prototype.(rx_post): Likewise.* config/rx-parse.y: Add v3 instructions and Double FPU registers.(DSIZE): Define.(POST): Define.(rx_check_v3): New. check v3 type.(rx_check_dfpu): New. check have double support.(double_condition_table): New. dcmp<cond> contiditon.(check_condition): Multiple condition support.(rx_lex): RXv3 instructions support.Add parse dcmp<cond> instruction and Double FPU registers.(immediate): Disable optimize in dmov #imm case.(displacement): Add double displacement in dmov instraction.* config/tc-rx.c (rx_use_conventional_section_names):Invert default value in rx-*-linux target.(cpu_type): Add additional ELF flags.(cpu_type_list): Add RXv3.(md_parse_option): Refer elf_flags from cpu_type_list.(md_show_usage): Add rxv3 and rxv3-dfpu.(rx_bytesT): Add post byte.(rx_bfield): New. generate bfmov / bfmovz "imm" field.(rx_post): New. Set instruction post byte.(md_assemble): Add post byte.doc/c-rx.texi: Add cpu types.* testsuite/gas/rx/Xtod.d: New.* testsuite/gas/rx/Xtod.sm: New.* testsuite/gas/rx/bfmov.d: New.* testsuite/gas/rx/bfmov.sm: New.* testsuite/gas/rx/dabs.d: New.* testsuite/gas/rx/dabs.sm: New.* testsuite/gas/rx/dadd.d: New.* testsuite/gas/rx/dadd.sm: New.* testsuite/gas/rx/dcmp.d: New.* testsuite/gas/rx/dcmp.sm: New.* testsuite/gas/rx/ddiv.d: New.* testsuite/gas/rx/ddiv.sm: New.* testsuite/gas/rx/dmov.d: New.* testsuite/gas/rx/dmov.sm: New.* testsuite/gas/rx/dmul.d: New.* testsuite/gas/rx/dmul.sm: New.* testsuite/gas/rx/dneg.d: New.* testsuite/gas/rx/dneg.sm: New.* testsuite/gas/rx/dpopm.d: New.* testsuite/gas/rx/dpopm.sm: New.* testsuite/gas/rx/dpushm.d: New.* testsuite/gas/rx/dpushm.sm: New.* testsuite/gas/rx/dround.d: New.* testsuite/gas/rx/dround.sm: New.* testsuite/gas/rx/dsqrt.d: New.* testsuite/gas/rx/dsqrt.sm: New.* testsuite/gas/rx/dsub.d: New.* testsuite/gas/rx/dsub.sm: New.* testsuite/gas/rx/dtoX.d: New.* testsuite/gas/rx/dtoX.sm: New.* testsuite/gas/rx/macros.inc: Add double FPU registers.* testsuite/gas/rx/mvfdc.d: New.* testsuite/gas/rx/mvfdc.sm: New.* testsuite/gas/rx/mvfdr.d: New.* testsuite/gas/rx/mvfdr.sm: New.* testsuite/gas/rx/mvtdc.d: New.* testsuite/gas/rx/mvtdc.sm: New.* testsuite/gas/rx/rstr.d: New.* testsuite/gas/rx/rstr.sm: New.* testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.* testsuite/gas/rx/save.d: New.* testsuite/gas/rx/save.sm: New.* testsuite/gas/rx/xor.d: New.* testsuite/gas/rx/xor.sm: Add pattern.2019-01-04 Wu Heng <wu.heng@zte.com.cn>PR 24010* macro.c (get_any_string): Check for end of input whilst scanningfor separators.2019-01-04 Wu Heng <wu.heng@zte.com.cn>PR 24009* read.c (stringer): Fix handling of missing '>' character at endof <...> sequence.2019-01-01 Alan Modra <amodra@gmail.com>Update year range in copyright notice of all files.For older changes see ChangeLog-2018Copyright (C) 2019 Free Software Foundation, Inc.Copying and distribution of this file, with or without modification,are permitted in any medium without royalty provided the copyrightnotice and this notice are preserved.Local Variables:mode: change-logleft-margin: 8fill-column: 74version-control: neverEnd: